Low Power Consumption Research Articles

High-precision reading of a weak magnetostatic field

Efforts have recently been put into developing proton precession magnetometers (PPM) in order to measure weak magnetic fields with high precision. Although high-cost commercial PPMs are available today, there are ongoing studies for low power consumption, low cost, high accuracy and resolution. Accordingly, in this study, a new PPM with a measurement range of 20,000 nT-120,000 nT, a production cost of $2000 and an accuracy of 0.13 nT was developed and its performance in determining the earth’s magnetic field was examined. It was determined that the developed PPM has an advantage over its commercial equivalents (G857, WCZ, etc.) in terms of price-performance ratio and can be used to determine small magnetic field values such as the earth’s magnetic field.

Analysis of the parasitic capacitance effects on the layout of latch-based sense amplifiers for improving SRAM performance

Static random-access memory (SRAM) technology is utilized in designing cache memory to enhance the processing performance of computer systems. The sense amplifier (SA) circuit, a crucial component of memory design, significantly impacts data access time and power consumption. In comparison to conventional differential sense amplifiers (DSA) designs, latch-based sense amplifiers (LSA) used in memory-based computing platforms have specific requirements, including robust noise resistance in harsh working environments and low power consumption, particularly for internet of thing (IoT) embedded computing applications. However, the performance can be degraded due to various factors that arise during the layout, such as conductor resistance or the development of parasitic capacitance. Therefore, this study employs low-voltage 22 nm UMC CMOS technology for LSA design layout and analyzes the factors influencing design performance post-layout process. Layout design optimization techniques are applied to mitigate the impact of parasitic capacitance on important signal lines such as data line/data line bar (DLL/DLLB). Based on the performance analysis results, it is possible to achieve a reduction in power consumption of up to 15% and a 5% decrease in read delay time by implementing circuit layout LSA design optimization techniques.

Machine learning algorithm partially reconfigured on FPGA for an image edge detection system

Unmanned aerial vehicles (UAVs) have been used for many applications including military, construction, image and video mapping, medical, search and rescue, wireless communications, and aerial surveillance. One key research topic involving UAVs is pose estimation in autonomous navigation. A standard procedure for this process for UAVs is to combine inertial navigation system (INS) sensor information with the global navigation satellite system (GNSS) signal. However, some factors can interfere with the GNSS signal, such as natural phenomena (ionospheric scintillation) or malicious attacks (jamming or spoofing). One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images. But a high effort is required for image edge extraction. In this paper, a support vector regression (SVR) model is proposed to reduce the computational load and processing time for image edge detection. The dynamic partial reconfiguration (DPR) of part of the SVR datapath was implementated to accelerate the process, reduce the area, and analyze its granularity aspect by increasing the grain size of the reconfigurable region. Results show that the implementation in hardware is 68 times faster than that in software. This kind of architecure with DPR also facilitates the low power consumption of 4 mW, leading to a reduction of 57 % compared with that without DPR, which is also the lowest power consumption compared with other machine learning (ML) hardware implementations. Besides, the circuitry area is 41 times smaller. SVR with Gaussian kernel showed a success rate of 99.18 % and minimum square error of 0.0146 for testing with the planning trajectory. This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application, thus contributing to lower power consumption, smaller hardware area, and shorter execution time.

Novel a-IGZO TFT Pixel Driving Circuit Using Hybrid PWM and PAM Method With Lower Power Consumption for Micro-LED Display

Novel a-IGZO TFT Pixel Driving Circuit Using Hybrid PWM and PAM Method With Lower Power Consumption for Micro-LED Display

Mo/Au β-Ga₂O₃ Schottky Barrier Diodes With Low Turn-On Voltage and High On–Off Ratios for Low-Power Consumption Applications

Mo/Au β-Ga₂O₃ Schottky Barrier Diodes With Low Turn-On Voltage and High On–Off Ratios for Low-Power Consumption Applications

Low-Power Consumption Control Method for BLDCM With Very Small Inductance and Nonideal Back EMF

Low-Power Consumption Control Method for BLDCM With Very Small Inductance and Nonideal Back EMF

LoRaWAN: The dilemma of optimal transmission parameter

Low-Power Wide-Area Network (LPWAN) technologies, particularly LoRaWAN, have gained significant attention for their ability to facilitate long-range communication with low power consumption, making them ideal for Internet of Things (IoT) applications. However, achieving optimal performance in LoRaWAN systems requires careful selection of transmission parameters such as spreading factor, bandwidth, and coding rate. This paper addresses the dilemma faced by network designers and operators in determining the optimal transmission parameters for LoRaWAN deployments. We provide an overview of the key parameters and their impact on network performance, considering factors such as latency, packet delivery rate, and energy efficiency. Furthermore, we discuss the trade-offs involved in parameter selection. Through simulations, we evaluate the performance of different parameter configurations under various network conditions and provide insights into achieving the best balance between coverage, capacity, and energy consumption in LoRaWAN deployments. Findings from the study established that using high coding rate and bandwidth only provides minimal improvement in packet delivery rate particularly at large distances but at the cost energy consumption while spreading factor remains the most important transmission parameter in LoRa networks.

Squaring Circuit Using 14nmFinFET Technology with Vedic Mathematics Approach

FinFET technology is an alternative to CMOS technology as in this technology device has higher drive current, speed, and low-power consumption. FinFET has better mobility and scaling than CMOS technology. A dedicated Squaring circuit is needed by many digital signal processors (DSP) and arithmetic and logical units (ALU). So fast, power-efficient, and compact squaring circuits can be designed with Vedic sutras. Vedic mathematics has 16 sutras and 13 sub-sutras that touch almost all different chapters of mathematics. Out of these sutras, Dwandwayoga has a duplex property that is used to find a square of an N-bit number. Also, Yavadunam is a special case for finding the square of a number that is closer to the base. This work targets a comparative analysis of these two square circuits having a Vedic approach with a conventional array multiplier. The proposed designs are implemented in micro-wind 3.9 electronic design automation tool (EDA) with 14 nm deep submicron technology post-layout. The values of model parameters are used from the current Berkeley 4 short channel model (BSIM4). It is observed that the proposed square architecture design using the Dwandwayog sutra and Yavadunam sutra achieves 185%, 272.45% delay depletion and a 122.22%, and 46.52% reduction in transistor requirements compared to the conventional array multiplier, respectively.

Inverse design of convolutional neural networks via nanophotonic kernels

We proposed an ultra-compact neural network based on inversely designed photonic kernels, which has the advantages of a small footprint, high computing speed, and low power consumption. The core layers of the neural network, composed of automatically optimized photonic multiplication kernels and addition kernels, can perform arbitrary photonic computations at the speed of the light wave, offering more advantages than their electronic counterparts. Furthermore, the convolution, pooling, and fully-connected layers can be realized by the appropriate permutation of the proposed optical kernels. We constructed an all-optical convolutional neural network with a high accuracy of 97.7% for recognizing handwritten digits. Our results could significantly promote the inverse design of photonic neural networks.

Domain wall magnetic tunnel junction-based artificial synapses and neurons for all-spin neuromorphic hardware

We report a breakthrough in the hardware implementation of energy-efficient all-spin synapse and neuron devices for highly scalable integrated neuromorphic circuits. Our work demonstrates the successful execution of all-spin synapse and activation function generator using domain wall-magnetic tunnel junctions. By harnessing the synergistic effects of spin-orbit torque and interfacial Dzyaloshinskii-Moriya interaction in selectively etched spin-orbit coupling layers, we achieve a programmable multi-state synaptic device with high reliability. Our first-principles calculations confirm that the reduced atomic distance between 5d and 3d atoms enhances Dzyaloshinskii-Moriya interaction, leading to stable domain wall pinning. Our experimental results, supported by visualizing energy landscapes and theoretical simulations, validate the proposed mechanism. Furthermore, we demonstrate a spin-neuron with a sigmoidal activation function, enabling high operation frequency up to 20 MHz and low energy consumption of 508 fJ/operation. A neuron circuit design with a compact sigmoidal cell area and low power consumption is also presented, along with corroborated experimental implementation. Our findings highlight the great potential of domain wall-magnetic tunnel junctions in the development of all-spin neuromorphic computing hardware, offering exciting possibilities for energy-efficient and scalable neural network architectures.

Bismuth-based ferroelectric memristive device induced by interface barrier for neuromorphic computing

The development of the Internet of Things (IoT) not only facilitates our lives but also dramatically grows data. Artificial synaptic devices appear to represent an emerging physical solution compared to the existing computational architectures. Memristive devices are of great interest with their high integration and low power consumption in the field of synaptic devices. In this work, we demonstrate short-term plasticity (STP) and long-term plasticity (LTP) by regulating synaptic weights with different stimulus pulses. Moreover, the application in neuromorphic computing is further exhibited by image recognition with an accuracy of 95.2 % under the modified National Institute of Standards and Technology database. Therefore, Nd-doped Bi4Ti3O12 memristors, as emerging artificial synaptic devices, are expected to achieve breakthroughs in artificial intelligence and promote the development of neuromorphic computing and intelligent systems.

Large Field-like Spin-Orbit Torque and Enhanced Magnetization Switching Efficiency Utilizing Amorphous Mo.

Spin-orbit torque magnetic random access memory (SOT-MRAM) has great promise in high write speed and low power consumption. Mo can play a vital role in constructing a CoFeB/MgO-based MRAM cell because of its ability to enhance the perpendicular magnetic anisotropy (PMA), thermal tolerance, and tunneling magnetoresistance. However, Mo is often considered as a less favorable candidate among SOT materials because of its weak spin-orbit coupling. In this study, we experimentally investigate the SOT efficiencies in Mo/CoFeB/MgO heterostructures over a wide range of Mo thicknesses and temperature. Decent damping-like SOT efficiency |ξDL| = 0.015 ± 0.001 and field-like SOT efficiency |ξFL| = 0.050 ± 0.001 are found in amorphous Mo. The ξFL/ξDL ratio is greater than 3. Furthermore, efficient current-induced magnetization switching is demonstrated with the critical current density comparable with heavy metal Ir and W. Our work reveals new understanding and possibilities for Mo as both an SOT source component and PMA buffer layer in the implementation of SOT-MRAMs.

Artificial Tactile Receptor System for Sensitive Pressure-Neural Spike Conversion.

An artificial tactile receptor is crucial for e-skin in next-generation robots, mimicking the mechanical sensing, signal encoding, and preprocessing functionalities of human skin. In the neural network, pressure signals are encoded in spike patterns and efficiently transmitted, exhibiting low power consumption and robust tolerance for bit error rates. Here, we introduce a highly sensitive artificial tactile receptor system integrating a pressure sensor, axon-hillock circuit, and neurotransmitter release device to achieve pressure signal coding with patterned spikes and controlled neurotransmitter release. Owing to the heightened sensitivity of the axon-hillock circuit to pressure-mediated current signals, the artificial tactile receptor achieves a detection limit of 10 Pa that surpasses the human tactile receptors, with a wide response range from 10 to 5 × 105 Pa. Benefiting from the appreciable pressure-responsive performance, the potential application of an artificial tactile receptor in robotic tactile perception has been demonstrated, encompassing tasks such as finger touch and human pulse detection.

Cation-Modified Poly(vinyl alcohol) Film to Optimize the Bistability of Transparent Electrophoretic Display Based on Charge Adsorption Behavior in Nonpolar Solvent.

Electrophoretic displays (EPDs) utilize the electrophoretic particles in electronic ink (e-ink) to display different color states with bistability. Bistability of EPDs is achieved by placing colloidal particles in a highly viscous solvent to keep the distribution of colloidal particles stable without sustaining the external field, so it only consumes power when updating the image. The feature of low power consumption makes it suitable for applications such as advertising boards, price tags, etc. Apart from these applications, recent research on lateral-driving EPDs extends its applications to smart windows, privacy control, and so on. However, achieving bistability by simply increasing the viscosity of solvent is inefficient in the case of lateral driving operation. Therefore, it is deserving to have intensive study on the mechanism of bistability from other aspects. Herein, we propose a mechanism to investigate the charge adsorption behavior on the electrode to affect the bistability of particles, which is based on the "Stern layer adsorption/desorption" model. Based on the above mechanism, we further fabricated a hexadecyl trimethylammonium bromide (CTAB)/poly(vinyl alcohol) (PVA) composite film on the electrode to improve the bistability of lateral-driving EPD by reducing the diffusion current caused by unabsorbed charges. This developed lateral-driving EPD can significantly improve the bistability, which is enhanced from 40 s to 7 min, an increase by a factor of approximately 10. This work gives a way to consider the bistability of colloidal particles in nonpolar solvent.

Neuromorphic Computing in Synthetic Antiferromagnets by Spin‐Orbit Torque Induced Magnetic‐Field‐Free Magnetization Switching

AbstractSynthetic antiferromagnet (SAF) with high thermal stability, ultra‐fast spin dynamics, and highly efficient spin‐orbit torque switching has great application potential in neuromorphic computing hardware. However, two challenges, the weakening of Hall signal in the remanent state and the need for a large auxiliary magnetic field for perpendicular magnetization switching, greatly limit the advantages of SAF in neuromorphic computing. In this work, both the enhanced anomalous Hall resistance and magnetic‐field‐free perpendicular magnetization switching are achieved by using oblique sputtering to fabricate the Pt/CoPt/Ru/CoTb SAF with strong interlayer exchange coupling and magnetic moment compensation. The fabricated SAF as synapse shows nearly linear, nonvolatile multistate plasticity, and as neuron exhibits a nonlinear sigmoid activation function, which are used to construct a fully connected neural network with a remarkable 97.0–98.1% recognition rate for the handwritten digits. Additionally, SAF serving as spike‐timing‐dependent plasticity synapse is used to construct an adaptive, unsupervised learning spiking neural network, and achieve an 87.0% accuracy in handwritten digit recognition. The findings exhibit the promise of SAFs as specialized hardware for high‐performance neuromorphic computing, offering high recognition rates and low power consumption.

High-Efficiency Vertical-Chip Micro-Light-Emitting Diodes via p-GaN Optimization and Surface Passivation

Micro-LEDs have found widespread applications in modular large-screen TVs, automotive displays, and high-resolution-density augmented reality glasses. However, these micron-sized LEDs experience a significant efficiency reduction due to the defects originating from the dry etching process. By controlling the current distribution via engineering the electrode size, electrons will be less concentrated in the defect region. In this work, we propose a blue InGaN/GaN compound parabolic concentrator micro-LED with a metallic sidewall to boost efficiency by combining both an optical dipole cloud model and electrical TCAD (Technology Computer-Aided Design) model. By merely modifying the p-GaN contact size, the external quantum efficiency (EQE) can be improved by 15.6%. By further optimizing the passivation layer thickness, the EQE can be boosted by 52.1%, which helps enhance the display brightness or lower power consumption.

Study of Fixed Point Message Scheduling Algorithm for In-Vehicle Ethernet

With the rapid development of advanced driver assistance systems (ADASs) and autonomous driving technology, in-vehicle networks are facing huge challenges in real-time operation and data loss. Traditional vehicle bus network systems such as LIN, CAN, and FlexRay are insufficient to meet the real-time requirements of intelligent connected vehicles. In-vehicle Ethernet meets the requirements of high reliability, low electromagnetic radiation, low power consumption, bandwidth allocation, low latency, and real-time synchronization of intelligent connected vehicles. In-vehicle Ethernet has become one of the trends in the next generation of in-vehicle network architecture. This research focuses on the delay problem existing in the real-time data transmission process of in-vehicle Ethernet, and innovatively proposes a fixed point message scheduling algorithm (FPMS) based on time-sensitive network (TSN) technology. By building an experimental platform based on the CANoe simulation tool, the high-efficiency message transmission performance of the fixed point message scheduling algorithm was verified. Experimental results show that the fixed point message scheduling algorithm proposed in this study improves message transmission efficiency by 66%, laying a solid foundation for improving the real-time and reliability performance of in-vehicle Ethernet.

Safeguarding the Internet of Things: Elevating IoT routing security through trust management excellence

This study presents an innovative IoT routing security model that integrates trust management to bolster network reliability, improve resilience against routing attacks, and isolate malicious activities. The model, emphasizing node behavior, reputation, and past performance, offers a nuanced approach to network security. Through comprehensive comparisons between dynamic and static models in IoT routing, the impact on crucial performance parameters, including throughput, packet delivery ratio, control traffic overhead, and energy consumption, is quantified. Simulations showcase the model's effectiveness in securing IoT communication, achieving an impressive 98 % accuracy in detecting and mitigating attacks. Comparative analysis against prior studies underscores its exceptional performance, particularly in identifying and classifying attack types such as wormhole, Sybil, and rank, alongside normal traffic. This trust-based IoT routing security model represents a substantial advancement in securing dynamic IoT environments, standing out as a valuable contribution. Noteworthy is its low average power consumption, contributing to its exceptional lightweight nature.

A Programmable Ambient Light Sensor with Dark Current Compensation and Wide Dynamic Range

Ambient light sensors are becoming increasingly popular due to their effectiveness in extending the battery life of portable electronic devices. However, conventional ambient light sensors are large in area and small in dynamic range, and they do not take into account the effects caused due to a dark current. To address the above problems, a programmable ambient light sensor with dark current compensation and a wide dynamic range is proposed in this paper. The proposed ambient light sensor exhibits a low current power consumption of only 7.7 µA in dark environments, and it operates across a wide voltage range (2–5 V) and temperature range (−40–80 °C). It senses ambient light and provides an output current proportional to the ambient light intensity, with built-in dark current compensation to effectively suppress the effects of a dark current. It provides a wide dynamic range over the entire operating temperature range with three selectable output-current gain modes. The proposed ambient light sensor was designed and fabricated using a 0.18 µm standard CMOS process, and the effective area of the chip is 663 µm × 652 µm. The effectiveness of the circuit was verified through testing, making it highly suitable for portable electronic products and fluorescent fiber-optic temperature sensors.

High‐Speed and Low‐Power 2 × 2 Thermo‐Optic Switch Based on Dual Silicon Topological Nanobeam Cavities

AbstractA 2 × 2 thermo‐optic (TO) switch using dual topological photonic crystal nanobeam (PCN) cavities on the silicon‐on‐insulator (SOI) platform is proposed and experimentally demonstrated. A Fano resonance is observed due to the interference between the topological interface state of the 1D topological PCN cavity and the Fabry‐Perot (F‐P) cavity mode formed between the two facets of the finitely long nanobeam waveguide. Thanks to the sharp rising edge of the spectral response of the Fano resonance and the high confinement of light in the topological PCN cavities, a 2 × 2 TO switch is realized with short switching time and low power consumption. The measured switching power is only 1.55 mW, and the rising time and the falling time are 3 and 5.6 µs, respectively in the on‐off switching experiments. To the best of the knowledge, this is the first time that a dual topological PCN structure is utilized to realize a high‐speed and low‐power TO switch, revealing the possibility of designing high‐performance reconfigurable optical devices and networks using topological photonics.