Low-power CMOS Voltage Reference Research Articles

A low-voltage, low-power voltage reference based on subthreshold MOSFETs

A novel low-voltage low-power CMOS voltage reference independent of temperature is presented in this design. After considering the combined effect of (1) a perfect suppression of the temperature dependence of mobility; (2) the compensation of the channel length modulation effect on the temperature coefficient, a temperature coefficient of 10 ppm/[Formula: see text]C is achieved. Moreover, by adopting the subthreshold MOSFETs, there are no resistors used in the proposed structure. Therefore, the maximum supply current measured at the maximum supply voltage is 70 nA and at 80[Formula: see text]C. The circuit can be used as a voltage reference for high performance and low power dissipation on a single chip.

A high-PSRR low-power CMOS voltage reference based on weighted VGS difference

A high PSRR CMOS voltage reference circuit suitable for applications with noisy environments like power telemetry solutions and system on a chip (SOC) integrations is presented. The reference voltage is generated based on the difference between weighted gate-to-source voltages (VGS) of MOS transistors operating in subthreshold region. The circuit PSRR is improved using a new circuit configuration which removes the need for a passive resistive branch to scale up VGS voltages. The PSRR is further enhanced by reordering the pole-zero locations of the PSRR transfer function and then using supply-independent biasing circuit. Implemented in a 0.18μm standard CMOS process, the circuit occupies an area of about 0.035mm2. The minimum supply voltage is 1.4V and the maximum temperature coefficient is about 82ppm/°C. The PSRR at 100Hz and 10MHz frequencies are approximately −70dB and −100dB respectively. Using a 1.8V supply voltage, it consumes at least 42nA and at most 125nA depending on operating temperature and process corners.

A low power CMOS voltage reference generator with temperature and process compensation

A low power CMOS voltage reference with process compensation is presented in TSMC 0.18-μm standard CMOS technology. Detailed analysis of the process compensation technique is discussed. The circuit...

A low power CMOS voltage reference based on body effect

A low power CMOS voltage reference based on body effect

A low-voltage low-power CMOS voltage reference based on subthreshold MOSFETs

This paper describes a CMOS voltage reference using only resistors and transistors working in weak inversion, without the need for any bipolar transistors. The voltage reference is designed and fabricated by a 0.18 μm CMOS process. The experimental results show that the proposed voltage reference has a temperature coefficient of 370 ppm/°C at a 0.8 V supply voltage over the temperature range of −35 to 85 °C and a 0.1% variation in supply voltage from 0.8 to 3 V. Furthermore, the supply current is only 1.5 μA at 0.8 V supply voltage.

A 300 nW, 15 ppm/$^{\circ}$C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

A low-power CMOS voltage reference was developed using a 0.35 mum standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745 mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/degC at best and 15 ppm/degC on average, in a range from - 20 to 80degC. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4-3 V, and the power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The power dissipation was 0.3 muW at 80degC. The chip area was 0.05 mm2 . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.

A low power CMOS voltage reference circuit with sub threshold MOSFETs

In this paper, a novel approach is proposed for the design of low power CMOS band gap reference circuit. In the literature, an inversion technique is proposed to make the voltage reference to be independent of temperature by using parasitic bipolar transistors. In the above technique, this paper proposes the use of MOSFETs operating in sub threshold region for generating a voltage with negative temperature coefficient. The performance of the proposed scheme is studied by implementing the band gap reference circuit for 1.2 V in TSMC035 CMOS process. Studies through Mentorgraphics IC station and Eldo simulator demonstrate that the proposed scheme has a voltage reference with temperature coefficient of less than 50 ppm/°C over the temperature range of −10°C to 120°C. The proposed scheme results in 18 times lesser area and dissipates ten times lower power compared with that using parasitic bipolar transistors. The circuit technique has been validated using both NMOS and PMOS diode connected sub threshold MOSFETs for generating voltages with negative temperature coefficient.

A low-voltage low-power voltage reference based on subthreshold MOSFETs

In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-μm CMOS technology, exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm/°C in the range -25 to +125°C. A brief study of gate-source voltage behavior with respect to temperature in subthreshold MOSFETs is also reported.