Low-power Clock Recovery Circuit Research Articles

A 5–10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package

This paper presents an energy-efficient I/O interface with a 3-D flip chip package. The I/O interface is composed of a transmitter and a receiver. The transmitter consists of a pseudo-random bit sequence generator and an output buffer. The receiver employs a full-rate forwarded-clock structure that is composed of a novel current-domain equalizing sampler with a 10 Gb/s sampling rate for data recovery and a low-power clock recovery circuit with dual-injection-locked oscillators. The proposed sampler utilizes a current sampling structure and merges a shunt-peaked amplifier with 20-GHz bandwidth for data recovery. Meanwhile, clock recovery implements a phase interpolator achieving phase deskew larger than one data unit interval. A 3-D flip chip package with silicon substrate is utilized for multiple I/O channels integration. The chip was fabricated in a 65-nm CMOS process in an area of 0.42 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measurement results show that the I/O interface can realize a 5-10-Gb/s data rate with bit error rate less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> across 5-mm redistribution layers in a silicon substrate whose loss is 3~4 dB at Nyquist bandwidth.

Low power clock recovery circuit for passive HF RFID tag

A low power clock recovery circuit for passive HF RFID tag is presented. The proposed clock recovery circuit, based on the architecture of Phase Locked Loop (PLL), is used to generate a stable syst...

Low power clock recovery circuit for passive HF RFID tag

A low power clock recovery circuit for passive HF RFID tag is presented. The proposed clock recovery circuit, based on the architecture of Phase Locked Loop (PLL), is used to generate a stable system clock when communication occurs from interrogator to tag with 100% ASK modulation. An envelope detector is designed to detect the incident power from interrogator and control the operating state of the proposed clock recovery circuit. Loop bandwidth of PLL circuits is minimized to reduce the frequency deviation when operating in frequency maintaining state. Furthermore, an initialization circuit for loop filter is also used to speed up locking during initial system power-on-reset. Prototype chips have been fabricated in 0.35 μm 2P4M CMOS technology. A total current consumption of 3 μA has been achieved in the frequency maintaining state. Measurement results show that, when communication occurs from interrogator to tag with 100% ASK modulation, clock recovery circuit generates a stable and consecutive system clock and has an inevitable frequency derivation of 7.5% when operating in frequency maintaining state.