Low-power Chip Design Research Articles

Energy Prediction Models and Distributed Analysis of the Grinding Process of Sustainable Manufacturing.

Grinding is a critical surface-finishing process in the manufacturing industry. One of the challenging problems is that the specific grinding energy is greater than in ordinary procedures, while energy efficiency is lower. However, an integrated energy model and analysis of energy distribution during grinding is still lacking. To bridge this gap, the grinding time history is first built to describe the cyclic movement during air-cuttings, feedings, and cuttings. Steady and transient power features during high-speed rotations along the spindle and repeated intermittent feeding movements along the x-, y-, and z-axes are also analysed. Energy prediction models, which include specific movement stages such as cutting-in, stable cutting, and cutting-out along the spindle, as well as infeed and turning along the three infeed axes, are then established. To investigate model parameters, 10 experimental groups were analysed using the Gauss-Newton gradient method. Four testing trials demonstrate that the accuracy of the suggested model is acceptable, with errors of 5%. Energy efficiency and energy distributions for various components and motion stages are also analysed. Low-power chip design, lightweight worktable utilization, and minimal lubricant quantities are advised. Furthermore, it is an excellent choice for optimizing grinding parameters in current equipment.

A 4x4 modified 8 T SRAM cell array using power gating technique

Low power chip design is focused due to increase in demand of portable battery devices which is involved in day to day life. The memory plays an important role in all silicon on chip devices. SRAM’s are most widely used memory in the VLSI devices due to it’s better performance compared to DRAM. In Recent years SRAM, plays a dominant part in chip design and becomes the crucial research due to the high demand by the use of battery operated devices. To make the circuit more efficient the design should be successively operated with low leakage power at sub-threshold regions. A modified 8 T SRAM cell is designed and simulated using Tanner 13.1 EDA tool.