Low Phase Noise Voltage-controlled Oscillator Research Articles

A 34.16–39.6 GHz low phase noise VCO for frequency‐modulated continuous‐wave radar in a 28‐nm CMOS

AbstractA dual‐core voltage‐controlled oscillator (VCO) using harmonic resonance is presented in this letter. Without an additional switch capacitor bank, harmonic resonance implemented in VCO is realized by only a single control voltage, satisfying the requirement of frequency‐modulated continuous‐wave radar. Two pairs of varactors are added to the transformer‐based tank, which ensures a constant ratio between the two resonant frequencies of the tank in the entire tuning range. Robustly single‐frequency oscillation is obtained by increasing the coupling coefficient of the transformer and the coupling capacitor's capacitance. Implemented in a 28‐nm complementary metal–oxide–semiconductor, the VCO shows a 14.75% frequency tuning range covering 34.16–39.6 GHz. The measured results show it exhibits −102.13 dBc/Hz phase noise at a 1 MHz offset from the 34.16 GHz. The oscillator core draws 21–28 mA from a 0.9 V supply.

A 56.6-63.1GHz LO generator with a low PN VCO and an ILFT

ABSTRACT In this paper, we propose an mm-wave local oscillator generation (LOG) method based on a voltage-controlled oscillator (VCO) with low phase noise (PN) and a novel injection-locked frequency tripler (ILFT), which can significantly improve the PN performance and power efficiency. The VCO features the source-to-gate feedback architecture with a third-impedance enhancement transformer so that the fundamental signal with the boosted third-harmonic output voltage in the source terminal is delivered to ILFT and the relatively pure 20-GHz signal from the gate node can be fed back to the phase-locked loop (PLL). The proposed ILFT adopts the high-order transformer-based resonator, injection-current-boosting (ICB), and class-D tail-switching techniques leading to a wide locking range (LR). Designed and simulated in 40-nm CMOS technology, the post-simulation results exhibit 1-MHz offset PN of better than −102 dBc/Hz over a continuous frequency tuning range (FTR) of 10.9% from 56.6 to 63.1 GHz while consuming 23.5 mW. The figure-of-merit (FoM) achieves up to 186.2 dBc/Hz at 1-MHz offset.

Design of 50-GHz Low Phase Noise VCO Employing Two-Branches DGS Resonator in 0.18-μm CMOS Technology

This letter presents a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> -band low phase noise voltage-controlled oscillator (VCO) design using a novel integrated two-branches defected ground structure (DGS) resonator in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> complementary metal-oxide-semiconductor (CMOS) technology. The proposed DGS resonator is realized in the top metal layer (M6) which has not only a higher quality factor than its predecessors but is also effective to reduce the length of interconnects. The measured carrier frequency and phase noise are 49 GHz and −122.05 dBc/Hz (−102.58 dBc/Hz) at 10-MHz (1-MHz) offset frequencies, respectively. The VCO core consumes 5.5 mW of dc power from the dc supply, which results in a figure of merit (FoM) of −189 dBc/Hz. The proposed VCO using the two-branches DGS resonator may give an alternative low-cost solution for designing a high-performance VCO or frequency synthesizer at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> -band and beyond.

Design of Low Phase Noise VCO Considering C/L Ratio of LC Resonator in 0.18-μm CMOS Technology

A voltage-controlled oscillator (VCO) is usually designed by maximizing the quality (Q-) factor of the LC-tank resonator to realize a low phase noise. For the same frequency, the ratio of C/L affects the loaded Q-factor (QL) and then phase noise of the VCO. This affect has not been considered so far in the design of VCO because the conventional on-chip spiral inductor cannot be optimized for C/L ratio. This brief first investigates the effects of C/L ratio on the phase noise, and a design methodology for optimized C/L ratio using defected ground structure (DGS) resonator is presented. Then, the resonators were further evaluated based on LgL-product simulation for a fixed Ibias. Employing the proposed resonator, a very low phase noise KUband VCO is designed and implemented in 0.18-lm CMOS technology. The measurement result shows that the proposed VCO has a phase noise of -110.77 dBc/Hz at 1 MHz offset of 17.5 GHz carrier frequency and a frequency tuning range of 8.7%. The VCO consumes 2.3 mW power, which results in a figure of merit (FoM) of -191.95 dB.

Low-power low-phase noise VCO for 24 ​GHz applications

In this paper, CMOS voltage controlled-oscillator (VCO) with a frequency range of 22.7 ​GHz–27.9 ​GHz is presented. The scheme is modified current-reuse configuration, applicable to 5G applications. In the proposed configuration, the transistors are biased in subthreshold vicinity (VGS ​< ​VTH) to reduce power consumption. The usage of the capacitive feedback technique helps the output voltage to swing over the positive supply voltage and beneath the potential ground. The inclusion of the cross-coupled NMOS transistors with the inductive source degeneration enhance the transconductance and phase noise performance of VCO. The VCO has been implemented using 65 ​nm CMOS technology. The proposed VCO baised with 0.9 ​V and it showed the lowest power consumption of 1.35 ​mW and the lowest phase noise of −117 ​dBc/Hz at the 1 ​MHz offset frequency as compared to conventional results. This circuit also showed wide tuning range of 26.4%, low FOMT of −194.3 ​dBc/Hz, and small area in core die of 0.35 ​mm ​× ​0.35 ​mm. In addition, we have analyzed the mesaured output power spectrum of the proposed VCO using spectrum analyser (Anritsu, MS2760A) whereas the measured output power of the designed VCO is −7.9 dBm at the frequency of 24.5 ​GHz.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

K-Band Low Phase Noise VCO Based on Q-Boosted Switched Inductor

In this article, the development of the K-band low phase noise voltage-controlled oscillator (VCO) based on Q-boosted switched inductor is presented. Compared with the conventional switched inductor, the eddy current will be decreased using a 2-turn secondary coil, and then the dissipated power from the switch on-resistance will also be decreased, leading to a boosted inductor Q at switch ON-state. The equivalent inductance, quality factor, and self-resonance frequency at switch ON/OFF states are analyzed and derived. For comparison, K-band VCOs have been designed and fabricated in a 130nm BiCMOS process with the Q-boosted and conventional switched inductors. Measured results show that the phase noise has been typically improved by 2–5dB at 100 kHz and 1 MHz offset at switch ON-state, using the Q-boosted switched inductor.

28-GHz CMOS VCO With Capacitive Splitting and Transformer Feedback Techniques for 5G Communication

This paper presents a 28-GHz low phase noise voltage-controlled oscillator (VCO) in a 65-nm CMOS process for 5G communication applications. With the capacitive splitting and transformer feedback techniques, theoretical analysis and simulations are undertaken for the proposed oscillator, proving that its negative G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> can be enhanced over the interested frequency range and reduced at the harmonic frequencies. Moreover, the proposed oscillator startup performance is analyzed, and its tank quality factor, transient and phase noise performance are simulated. With 4-bit switch capacitors and varactors, the proposed VCO achieves a tuning range from 25.7 to 29.7 GHz, consuming 10.8 mW from a 0.9-V supply voltage. With a wideband common-source buffer, the output signal power is around 1 dBm. At 26.5 GHz, the proposed VCO achieves low phase noise of -105.8 dBc/Hz at 1-MHz offset and -130 dBc/Hz at the 10-MHz offset, respectively.

A compact 0.045–2.3 GHz frequency synthesizer with a wide tuning range low phase noise VCO for software defined radios

A compact 0.045–2.3 GHz wideband fractional-N frequency synthesizer (FS) for software defined radios (SDR) applications is presented in this paper. Based on a single phase locked loop (PLL) that employs one integrated inductor-capacitor voltage controlled oscillator (VCO), the proposed FS can provide a wide operating frequency range. The VCO adopts an optimized circular inductor to mitigate the phase noise degradation caused by the high VCO gain. The in-band phase noise is optimized by employing current mode logic dividers and true single phase clock dividers. The PLL provides the differential outputs ranging from 2.3 to 4.6 GHz and the 0.045–2.3 GHz quadrature local oscillator signals are generated by the following divider chain. The proposed FS is implemented in TSMC 180 nm RFCMOS process and provides a phase noise performance less than − 116 dBc/Hz at 1 MHz offset. The maximum power consumption is 54 mW. The die size including pads and I/O is 1.92 mm2 with an active core area of 1.13 mm2. This proposed circuit has the great potential for SDR applications.

CMOS Active Inductor Based Voltage Controlled Oscillator

&lt;p class="MsoNormal" style="margin-top: 6.0pt; text-align: justify;"&gt;&lt;span style="font-size: 9pt;" lang="EN-IN"&gt;A Tunable Active Inductor (TAI) based Voltage Controlled Oscillator (VCO) for Radio Frequency (RF) applications ranging from 670 MHz - 1.53 GHz is presented. A design of low phase noise and compact VCO is proposed. In order to lower the phase noise of VCO, its RF output power has been improved. The use of low voltage active in-ductor circuit reduces the power dissipation of VCO. The single ended CMOS active inductors with minimum number of transistors are used to consume less die area of VCO circuit. The low power dissipation of the circuit have high efficiency to generate output RF power. A supply independent variable current source tunes the VCO. The post layout design is simulated in Cadence spectreRF using TSMC 180 nm process libraries. The VCO circuit shows the phase noise variation from -124 to - 126 dBc/Hz and an active area of 0.0049 mm&lt;sup&gt;2&lt;/sup&gt;. The VCO core circuit, excluding output buffers, consumes 10 mW at 1.8 V supply voltage.&lt;/span&gt;&lt;/p&gt;

Low Phase-noise Voltage-controlled Oscillator for Wireless Personal Area Networks

Low Phase-noise Voltage-controlled Oscillator for Wireless Personal Area Networks

Wide tuning range low phase noise VCO for V‐band application

In this study, millimetre wave (MMW) voltage controlled oscillator (VCO) is designed using 130 nm complementary metal–oxide–semiconductor single poly eight metals (1P8M) technology. Under 0.8 V supply, VCO can be tuned from 46 to 61.2 GHz, i.e. 28% frequency tuning range (FTR) is achieved. For the highest oscillation frequency, phase noise at 10 MHz offset frequency is −117.3 dBc/Hz, while the power dissipation is 9.39 mW. The FTR is improved by adopting multiband scheme using transformer tuned technique. Improvement in phase noise is done with a P-type metal–oxide–semiconductor as a variable capacitor for fine tuning of each band. Single N-type metal–oxide–semiconductor switch is placed on secondary side of transformer which makes the transformer tunable. Figure of merit of the proposed circuit is −183.3 dBc/Hz. Proposed VCO provides wide FTR and acceptable low phase noise for V-band application.

Design and Application of Virtual Inductance of Square-Shaped Defected Ground Structure in 0.18- $\mu \text{m}$ CMOS Technology

This paper investigates a possibility of application of a virtual inductor realized by an integrated defected ground structure (DGS) to design a front-end circuit in CMOS technology. Two types of DGS are analyzed and found that the inductance realized by a square-shaped DGS achieves smaller size and higher quality factor than an H-shaped DGS. Then, a 15-GHz low phase noise voltage-controlled oscillator (VCO) employing the proposed square-shaped DGS in 0.18- $\mu \text{m}$ 1P6M CMOS technology is designed. The fabricated VCO operates from 15.2 to 16.12 GHz and consumes 5-mW power. The measured phase noise is −132.08 dBc/Hz at 10-MHz offset frequency, and this results in the figure of merit (FoM) and FoM taking account of the area to be 189.1 and 199.9 dB, respectively.

A Low Phase Noise VCO Based on Substrate-Integrated Suspended Line Technology

This letter presents a low phase noise voltage-controlled oscillator (VCO) based on substrate-integrated suspended line (SISL) technology. With the proposed SISL technology, high-Q resonators and inductors can be realized to improve the phase noise performance. In addition, a transformed radial stub resonator is adopted to stabilize frequency and to make the circuit compact at the same time. The designed VCO achieved a phase noise of −132 dBc/Hz at 1-MHz offset from a 4.16-GHz carrier with an output power around 4.6 dBm. And the VCO size is only $28.94 \times 20.75$ mm2. Compared to other board level VCOs, this design has low phase noise, low power consumption, and compact size with the features of self-package simultaneously.

Phase noise analysis of voltage controlled oscillator used in cesium atomic clock

Coherent population trapping (CPT) cesium frequency standard plays a significant role in precision guidance of missile and global positioning system (GPS). Low noise 4.596 GHz voltage controlled oscillator (VCO) is an indispensable part of microwave signal source in cesium frequency standard. Low-phase noise is also the most important and difficult performance indicator of VCO. Starting from phase noise analysis method proposed by Leeson, the formulas about the relationship between phase noise of output signal of oscillator feedback model and phase fluctuation spectrum of amplifier, phase noise of oscillator are derived in this paper. Finally, the asymptote model of microwave oscillator is proposed based on the formula derivation. The experiment shows that when the reverse bias voltage of variode is 1.8 V, the designed oscillation frequency of VCO is 4.596 GHz, the power is −1 dBm and the DC power consumption is 19.6 mW. The tendency of phase noise simulation curve and actual test curve conform to asymptote model. The phase noise in 1 and 10 kHz is, respectively, −60.86 and −86.58 dBc/Hz. The significance of the paper lies in determining the main factors influencing oscillator phase noise and providing guiding direction for the design of low-phase noise VCO.

A Low Phase Noise, Low Power and Wide Tuning Range VCO with Filtering Technique in ISM Band

In this paper, a novel voltage controlled oscillator (VCO) with low phase noise, low power consumption and wide tuning range in the industrial, scientific and medical (ISM) band is proposed for communication systems applications. For improving the phase noise, filtering technique is used and VCO is designed with TSMC CMOS 0.18 μm technology and the power supply is 1.5 V. The simulation results with advanced design system (ADS) shows that phase noise in 1 MHz offset frequency from the carrier is -122 dBc/Hz and tuning range is 2 to 2.8 GHz. The power consumption of the core is 2.49 mW.

A Low Phase Noise, Low Power and Wide Tuning Range VCO with Filtering Technique in ISM Band

In this paper, a novel voltage controlled oscillator (VCO) with low phase noise, low power consumption and wide tuning range in the industrial, scientific and medical (ISM) band is proposed for communication systems applications. For improving the phase noise, filtering technique is used and VCO is designed with TSMC CMOS 0.18 μm technology and the power supply is 1.5 V. The simulation results with advanced design system (ADS) shows that phase noise in 1 MHz offset frequency from the carrier is -122 dBc/Hz and tuning range is 2 to 2.8 GHz. The power consumption of the core is 2.49 mW.

Design of a Low Phase Noise VCO for Rubidium Atomic Frequency Standard

Compared to the size and the power consumption of the traditional atomic clocks, the ones based on coherent population trapping (CPT) can provide improvement by two orders of magnitude in both aspects above, making them needed urgently in many fields. Among different CPT atomic clocks, the one made with the rubidium atom are used widely, and their operating performance largely depends on its internal voltage-controlled oscillator (VCO) which is used to provide a proper microwave signal. Based on this, a small size and low phase noise 3.035GHz VCO is designed with a modified Clapp circuit topology using low-cost surface-mount components, including a coaxial resonant (COAX) with high quality factor. The designed VCO is simulated and optimized with the combined use of the negative resistance analysis method and the transmission analysis with a virtual-ground. In order to obtain the desired results, different values of key capacitor elements are tried according to their concrete influences on the VCO during the process of the circuit tuning. The test results show that the phase noises of the VCO are -60.49dBc/Hz@300Hz, -73.08dBc/Hz@1KHz and -97.48dBc/Hz@10KHz, the output power is -1.13dBm and the voltage-controlled tuning sensitivity is about 12MHz/V.

MEMS-based LC tank with extended tuning range for low phase-noise VCO

This paper presents the modeling, manufacturing, and testing of a micro-electromechanical system (MEMS)-based LC tank resonator suitable for low phase-noise voltage-controlled oscillators (VCOs). The device is based on a variable MEMS varactor in series with an inductive coplanar waveguide line. Two additional parallel stubs controlled by two ohmic MEMS switches have been introduced in order to increase the resonator tunability. The device was fabricated using the FBK-irst MEMS process on high resistivity (HR) silicon substrate. Samples were manufactured with and without a 0-level quartz cap. The radio frequency characterization of the devices without 0-level cap has shown a continuous tuning range of 11.7% and a quality factor in the range of 33–38. The repeatability was also tested on four samples and the continuous tuning is 11.7 ± 2%. Experimental results on the device with a 0-level cap, show a frequency downshift of about 200 MHz and a degradation of the quality factor of about 20%. This is, most likely, due to the polymeric sealing ring as well as to a contamination of the ohmic contacts introduced by the capping procedure. A preliminary design of a MEMS-based VCO was performed using Advanced Design System and a hardwired prototype was fabricated on Surface Mount Technology on RO4350 laminate. The prototype was tested resulting in a resonance frequency of 5 GHz with a phase noise of −105 and −126 dBc at 100 KHz and 1 MHz, respectively, and a measured output power of −1 dBm.

Design and analysis of a three-stage voltage-controlled ring oscillator

This paper describes a large tuning range low phase noise voltage-controlled ring oscillator (ring VCO) based on a different cascade voltage logic delay cell with current-source load to change the current of output node. The method for optimization is presented. Furthermore, the analysis of performance of the proposed ring VCO is confirmed by the measurement results. The three-stage proposed ring VCO was fabricated in the 180-nm CMOS process of SMIC. The measurement results show that the oscillator frequency of the ring VCO is from 0.770 to 5.286 GHz and the phase noise is 97.93 dBc/Hz at an offset of 1 MHz from 5.268 GHz with a total power of 15.1 mW from a 1.8 V supply while occupying only 0.00175 mm2 of the core die area.