Low-level Bit Research Articles

CPFloat: A C Library for Simulating Low-precision Arithmetic

One can simulate low-precision floating-point arithmetic via software by executing each arithmetic operation in hardware and then rounding the result to the desired number of significant bits. For IEEE-compliant formats, rounding requires only standard mathematical library functions, but handling subnormals, underflow, and overflow demands special attention, and numerical errors can cause mathematically correct formulae to behave incorrectly in finite arithmetic. Moreover, the ensuing implementations are not necessarily efficient, as the library functions these techniques build upon are typically designed to handle a broad range of cases and may not be optimized for the specific needs of rounding algorithms. CPFloat is a C library for simulating low-precision arithmetics. It offers efficient routines for rounding, performing mathematical computations, and querying properties of the simulated low-precision format. The software exploits the bit-level floating-point representation of the format in which the numbers are stored and replaces costly library calls with low-level bit manipulations and integer arithmetic. In numerical experiments, the new techniques bring a considerable speedup (typically one order of magnitude or more) over existing alternatives in C, C++, and MATLAB. To our knowledge, CPFloat is currently the most efficient and complete library for experimenting with custom low-precision floating-point arithmetic.

Ultrasonic wireless communication using capacitive micromachined ultrasonic transducers in liquid with OOK digital modulation

The modulation scheme of ultrasonic communication using capacitive micromachined ultrasonic transducers, acting as the transmitted port and received port, was simulated and experimented with four parallel channels in silicone oil. Four channel signals were coded by a steady and reliable binary amplitude shift keying method such as on–off keying modulation. The modulation scheme was simulated with additive Gaussian noise and attenuated for every channel in silicone oil, and the sound attenuation influence was evaluated with different distances. The capacitive micromachined ultrasonic transducers were measured to achieve a −6 dB bandwidth of 305 kHz when operating in silicone oil. The channels were operated at different frequencies ranging from 300 kHz to 600 kHz with a channel spacing of 100 kHz. The bit rate of 50 kbps for one channel was achieved with a data rate of 200 kbps over a short-range distance of 0.1 m. The proposed correction coefficient could be used to adjust the threshold. The high overall signal-to-noise ratio of 29.41 dB ensured the system to have a low-level bit error rate.

Fast Approximations of Activation Functions in Deep Neural Networks when using Posit Arithmetic.

With increasing real-time constraints being put on the use of Deep Neural Networks (DNNs) by real-time scenarios, there is the need to review information representation. A very challenging path is to employ an encoding that allows a fast processing and hardware-friendly representation of information. Among the proposed alternatives to the IEEE 754 standard regarding floating point representation of real numbers, the recently introduced Posit format has been theoretically proven to be really promising in satisfying the mentioned requirements. However, with the absence of proper hardware support for this novel type, this evaluation can be conducted only through a software emulation. While waiting for the widespread availability of the Posit Processing Units (the equivalent of the Floating Point Unit (FPU)), we can already exploit the Posit representation and the currently available Arithmetic-Logic Unit (ALU) to speed up DNNs by manipulating the low-level bit string representations of Posits. As a first step, in this paper, we present new arithmetic properties of the Posit number system with a focus on the configuration with 0 exponent bits. In particular, we propose a new class of Posit operators called L1 operators, which consists of fast and approximated versions of existing arithmetic operations or functions (e.g., hyperbolic tangent (TANH) and extended linear unit (ELU)) only using integer arithmetic. These operators introduce very interesting properties and results: (i) faster evaluation than the exact counterpart with a negligible accuracy degradation; (ii) an efficient ALU emulation of a number of Posits operations; and (iii) the possibility to vectorize operations in Posits, using existing ALU vectorized operations (such as the scalable vector extension of ARM CPUs or advanced vector extensions on Intel CPUs). As a second step, we test the proposed activation function on Posit-based DNNs, showing how 16-bit down to 10-bit Posits represent an exact replacement for 32-bit floats while 8-bit Posits could be an interesting alternative to 32-bit floats since their performances are a bit lower but their high speed and low storage properties are very appealing (leading to a lower bandwidth demand and more cache-friendly code). Finally, we point out how small Posits (i.e., up to 14 bits long) are very interesting while PPUs become widespread, since Posit operations can be tabulated in a very efficient way (see details in the text).

TextMap: A general purpose visualization system

Human language is a versatile tool for communicating mental models between speakers of a language. This paper presents the TextMap system, a logic-based system for generating visuospatial representations from textual input. TextMap combines a minimalistic parser with a simple model counting mechanism to automatically extract coordinate information from propositional Horn-logic knowledge bases encoding spatial predications. The system is based on a biologically inspired low-level bit vector mechanism, the activation bit vector machine (ABVM). It does not require an ontology apart from a list of which tokens indicate relations. Its minimalism and simplicity make it a general purpose visualization or imagery tool. The paper describes the TextMap application architecture as well as the key algorithms forming the ABVM core. The system is evaluated with respect to a larger case study of a geographic layout of 13 cities demonstrating capabilities as well as current shortcomings for a complex scenario of a human mental map description.

High capacity secret image sharing using multilayer image steganography with primary cover predictive error

Image steganography is the art of hiding secret message in greyscale or cover images. Easy detection of secret message for any state-of-art image steganography can break the stego system. To prevent the breakdown of the stego system two tier data hiding is used. In this paper, we propose a high capacity image steganography with greyscale primary cover. Predictive primary cover (PPC) is computed from the primary cover using median edge detector (MED) predictor. Predictive error (PE) is the difference between primary cover and the PPC. The high level bit planes of the secret image (payload) are X-ORed with low level bit planes of the PPC and vice-verse. The resulting Stego image is embedded in a secondary cover image using bit plane X-OR algorithm. The cover image used is an RGB colour image. The proposed steganography scheme enhances the level of security of the existing bit plane X-OR algorithm without considerably increasing the computation time and detectability. The experimental results show that the proposed scheme achieves higher level of security with high embedding capacity. Higher level of security achieved by the proposed multilayer steganography scheme enhances the performance and security of the bit plane X-OR algorithm.

High capacity secret image sharing using multilayer image steganography with primary cover predictive error

Image steganography is the art of hiding secret message in greyscale or cover images. Easy detection of secret message for any state-of-art image steganography can break the stego system. To prevent the breakdown of the stego system two tier data hiding is used. In this paper, we propose a high capacity image steganography with greyscale primary cover. Predictive primary cover PPC is computed from the primary cover using median edge detector MED predictor. Predictive error PE is the difference between primary cover and the PPC. The high level bit planes of the secret image payload are X-ORed with low level bit planes of the PPC and vice-verse. The resulting Stego image is embedded in a secondary cover image using bit plane X-OR algorithm. The cover image used is an RGB colour image. The proposed steganography scheme enhances the level of security of the existing bit plane X-OR algorithm without considerably increasing the computation time and detectability. The experimental results show that the proposed scheme achieves higher level of security with high embedding capacity. Higher level of security achieved by the proposed multilayer steganography scheme enhances the performance and security of the bit plane X-OR algorithm.

An efficient bit plane X-OR algorithm for irreversible image steganography

The science of hiding secret information in a message is known as steganography; hence, the presence of secret information is concealed. It is the method of hiding cognitive content in same or another media to avoid detection by intruders. This paper introduces a new method wherein irreversible steganography is used to hide an image in the same medium so that the secret data is masked. The secret image is known as a payload and the carrier is known as a cover image. X-OR operation is used amongst mid level bit planes of carrier image and high level bit planes of secret image to generate new low level bit planes of the stego image. Recovery process includes the X-ORing of low level bit planes and mid level bit planes of the stego image. Based on the result of the recovery, subsequent secret image is generated. An RGB colour image is used as carrier and the secret image is a grayscale image of dimensions less than or equal to the dimensions of the carrier image. The proposed method greatly increases the embedding capacity without significantly decreasing the PSNR value.

Standardized active measurements an a tier 1 IP backbone

Synthetic or active measurements are often used to characterize IP performance; however, it is rare to find them used to resolve problems in an operational setting. We show that the active monitoring system in the AT&T IP backbone provide's a comprehensive view of network performance that is complementary to traditional element level monitoring, making it an integral part of network management. This paper discusses the design and implementation of these active measurements in the network. We continuously monitor "path-level" performance metrics such as round-trip delay, loss, jitter, and reordering events to proactively detect impairments. Our system relies on the promotion of key metrics to the operational displays, while maintaining a rich set of statistics for analyzing rare and unforeseen events. This timely information enables us to react,quickly to performance degradation, avoiding any sustained effect on customer applications. The results also help us understand the network's ability to support time-sensitive application performance. Selected "interesting" events observed are presented, including detection of degradation caused by low-level bit errors on a physical link, detection of route changes on the network and their impact on real-time applications, and finally detection of reordering caused by forwarding loops.

An experimental mixed purpose network

This paper deals with an experimental network application. As an example, an environment with on screen display of low density information is selected. Such an environment can be found in hospitals where patients have to be guided from one place to another, as well as in many other situations, like airports. The method used is a fiber based 20 Mbit/sec network. In order to have a homogeneous structure transputer links are used throughout. Both, packet oriented inter processor communications and low level bit streams for the video frames, can coexist over these links. Uniformity in the physical layer [1] ensures maximum reliability and flexibility. With the usage of transputer links, fault detection in this application is inherent. The overall design is a highly distributed and low cost solution. Interfaces to standard networks are easily available.

A high speed software implementation of the Data Encryption Standard

This paper describes a very fast software implementation of the Federal Data Encryption Standard (DES) for the 80–786 processor family. The complex instruction set of this processor family is exploited to implement the low-level bit manipulation of the DES in an efficient manner. A 386/33 MHz PC is capable of data rates of over 200 kpbs, including time taken to read from and write to hard disk.