Low Equivalent Oxide Thickness Research Articles

Stabilization of Morphotropic Phase Boundary in Hafnia via Microwave Low‐Temperature Crystallization Process for Next‐Generation Dynamic Random Access Memory Technology

The morphotropic phase boundary (MPB), which arises from the combination of antiferroelectric and ferroelectric phases, demonstrates the highest dielectric constant (κ) compared to other phases. This emphasizes its potential as a leading contender for dielectric films in future dynamic random access memory (DRAM) capacitors. MPB‐based high‐κ materials using hafnia have shown a trade‐off between equivalent oxide thickness (EOT) and leakage current density (Jleak) when the crystallization temperature increases with scaling the thickness. Herein, a microwave annealing (MWA) method that can achieve low‐temperature crystallization below 350 °C is employed. The purpose of this method is to mitigate the trade‐off relationships and achieve the strict criteria of current DRAM capacitors. These criteria include low EOT (less than 4 Å) and Jleak (less than 10−7 A cm−2 at 0.8 V) characteristics. The MWA is capable of relatively low‐temperature annealing by supplying energy to the films through both thermal energy and dipole vibration energy. As a result, a record‐low EOT of 3.76 Å and a low leakage current characteristic of 4.2 × 10−8 A cm−2 at 0.8 V are achieved concurrently. It is confident that the research can be important in addressing the challenges associated with reducing the size of next‐generation DRAM capacitors.

Low temperature crystallization of atomic-layer-deposited SrTiO3 films with an extremely low equivalent oxide thickness of sub-0.4 nm

Despite SrTiO3(STO) possessing a high dielectric constant, its application as a capacitor dielectric in dynamic random-access memory(DRAM) capacitors faces challenges due to the high-temperature annealing for crystallization, its compositional inhomogeneity, and the high leakage currents of STO films. To address these issues, we employ atomic layer deposition(ALD) of STO films onto Pt substrates at elevated temperatures(340–380 °C). The use of low-reactivity Pt electrodes effectively mitigates the initial growth of excess Sr, ensuring enhanced compositional uniformity along the film growth direction. Coupled with ALD at high temperatures, this approach facilitates the crystallization of STO films in the as-grown state, further enhancing the crystallinity with increasing film thickness. Subsequent low-temperature post-deposition annealing (PDA) at 400 and 500 °C achieves full crystallization. This process results in a remarkable increase in the dielectric constant, reaching approximately 150. Furthermore, the absence of microcracks after PDA, attributed to the formation of adequately dense films, contributes to substantially improved dielectric properties. Consequently, these STO films exhibit an exceptionally low equivalent oxide thickness of 0.34 nm coupled with an ultralow leakage current of 3.7 × 10−8 A/cm2 at an operation voltage of 0.8 V, promising for advancing DRAM capacitors. This study presents a pathway for the sustainable scaling of DRAMs, addressing challenges in ALD-grown STO films.

Correlation of interfacial and dielectric characteristics in atomic layer deposited Al2O3/TiO2 nanolaminates grown with different precursor purge times

Considering the potential applications of Al2O3/TiO2 nanolaminates (ATA NLs) in storage capacitors, device-grade ATA NLs are fabricated using an ALD system, wherein the effect of precursor purging time on interfacial, and dielectric properties is thoroughly investigated. With an increase in half-cycle purging time from 2 to 4 s, the observed improvement in interface quality and sublayer density of these NLs is ascribed to the efficient removal of reaction by-products and impurities. Moreover, with an increase in purge time from 2 to 4 s, the increase in dielectric constant and concurrent decrease in dielectric loss from ∼132 to 154 and from ∼0.29 to 0.2, respectively, are primarily assigned to the improvement in sublayer conductivity contrast assisted Maxwell–Wagner interfacial polarization across Al2O3/TiO2 interfaces. The NL based devices fabricated at 4 s purging time, exhibited a capacitance density of ∼18.94 fF/μm2, low equivalent oxide thickness of ∼1.82 nm, and reduced leakage current density of ∼3.04 × 10−5 A/cm2 at 2 V applied bias, which demonstrates its suitability as high-k materials for energy storage applications. Furthermore, this study not only gives an insight of the purging time induced growth chemistry of ATA NLs but also explores the possibility of improving its dielectric performance essential for multifaceted applications.

High-κ Hf0.3Zr0.7O2 film with morphotropic phase boundary for DRAM capacitor by controlling H2O dose

For the miniaturization of dynamic random-access memory (DRAM), it is necessary to obtain low equivalent oxide thickness (EOT) and low leakage capacitor materials with complementary metal-oxide semiconductor (CMOS) process compatibility. Herein, we explore the influence of the dose of H2O reactants on the phase structure and electrical characteristics of Hf0.3Zr0.7O2 (HZO) thin films during the atomic layer deposition (ALD). By controlling the H2O dose as well as other conditions including inserting alumina, adjusting annealing temperature and electric field cycling, a high dielectric constant of ∼45 (EOT ∼ 0.54 nm) and low leakage current density (<7.7 × 10−8 A/cm2 at ±0.5 V) are achieved in the TiN/Al2O3 (∼0.3 nm)/Hf0.3Zr0.7O2 (∼6 nm)/TiN capacitor near the morphotropic phase boundary (MPB). Furthermore, the dielectric constant remains above 40 with endurance >1012 cycles (even extrapolated to 1015 cycles under voltage pulse of 0.5 V @10 MHz) at both room temperature and 85 °C. These results are helpful for achieving a high dielectric constant and low leakage for future generation DRAM capacitor materials.

The Effects of Postdeposition Anneal and Postmetallization Anneal on Electrical Properties of TiN/ZrO2/TiN Capacitors

Metal–insulator–metal (MIM) capacitors based on zirconia (ZrO2) are widely used in dynamic random access memories (DRAMs). As the smaller and smaller feature size in DRAM chips requires higher and higher capacitance density, it is necessary to minimize the equivalent oxide thickness (EOT) of ZrO2, or maximize its dielectric constant ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> ) while maintaining low leakage currents. Annealing is an effective method to achieve high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> -values. In this article, we report the impact of two mainstream annealing methods on the electrical properties of ZrO2-based MIM capacitors. The results showed that the dielectric constant of ZrO2 reached 41.5 after postdeposition anneal (PDA) at 350 °C, while grazing incidence X-ray diffraction (GIXRD) measurements indicated the formation of high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> tetragonal phase. In contrast, similar dielectric constant enhancement requires much higher temperature (450 °C) for postmetallization anneal (PMA). When similar high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> value was reached, the leakage current density of PDA samples was three orders of magnitude lower than that of PMA ones at 0.8 V. Additionally, lower annealing temperature also decreases the parasitic EOT at the interface, which was formed by the interaction of ZrO2 and TiN electrodes. Overall, we found PDA is more beneficial for achieving a higher dielectric constant (>40), lower leakage currents, and lower EOT at lower temperatures compared with PMA, and potentially more suitable for industrial DRAM fabrication process.

Process temperature-dependent interface quality and Maxwell-Wagner interfacial polarization in atomic layer deposited Al2O3/TiO2 nanolaminates for energy storage applications.

Considering the excellent tunability of electrical and dielectric properties in binary metal oxide based multi-layered nanolaminate structures, a thermal atomic layer deposition system is carefully optimized for the synthesis of device grade Al2O3/TiO2 nanolaminates with well-defined artificial periodicity and distinct interfaces, and the role of process temperature in the structural, interfacial, dielectric and electrical properties is systematically investigated. A marginal increase in interfacial interdiffusion in these nanolaminates, at elevated temperatures, is validated using X-ray reflectivity and secondary ion mass spectrometry studies. With an increase in deposition temperature from 150 to 300 °C, the impedance spectroscopy measurements of these nanolaminates exhibited a monotonic increment in dielectric constant from ∼95 to 186, and a decrement in dielectric loss from ∼0.48 to 0.21, while the current-voltage measurements revealed a subsequent reduction in leakage current density from ∼2.24 × 10-5 to 3.45 × 10-7 A cm-2 at 1 V applied bias and an improvement in nanobattery polarization voltage from 100 mV to 700 mV, respectively. This improvement in dielectric and electrical properties at elevated processing temperature is attributed to the reduction in impurity content along with the significant enhancement in sublayer densities and the conductivity contrast driven Maxwell-Wagner interfacial polarisation. Additionally, the devices fabricated at 300 °C exhibited a higher capacitance density of ∼22.87 fF μm-2, a low equivalent oxide thickness of ∼1.51 nm, and a low leakage current density of ∼10-7 A cm-2 (at 1 V bias), making this nanolaminate a promising material for high-density energy storage applications. These findings highlight the ALD process temperature assisted growth chemistry of Al2O3/TiO2 nanolaminates for superior dielectric performance and multifaceted applications.

Novel Approach to High κ (∼59) and Low EOT (∼3.8 Å) near the Morphotrophic Phase Boundary with AFE/FE (ZrO2/HZO) Bilayer Heterostructures and High-Pressure Annealing.

We present herewith a novel approach of equally thick AFE/FE (ZrO2/HZO) bilayer stack heterostructure films for achieving an equivalent oxide thickness (EOT) of 4.1 Å with a dielectric constant (κ) of 56 in complementary metal-oxide semiconductor (CMOS) compatible metal-ferroelectric-metal (MFM) capacitors using a high-pressure annealing (HPA) technique. The low EOT and high κ values were achieved by careful optimization of AFE/FE film thicknesses and HPA conditions near the morphotropic phase boundary (MPB) after field cycling effects. Stable leakage current density (J < 10-7 A/cm2 at ±0.8 V) was found at 3/3 nm bilayer stack films (κ = 56 and EOT = 4.1 Å) measured at room temperature. In comparison with previous work, our remarkable achievement stems from the interfacial coupling between FE and AFE films as well as a high-quality crystalline structure formed by HPA. Kinetically stabilized hafnia films result in a small grain size in bilayer films, leading to reducing the leakage current density. Further, a higher κ value of 59 and lower EOT of 3.4 Å were found at 333 K. However, stable leakage current density was found at 273 K with a high κ value of 53 and EOT of 3.85 Å with J < 10-7 A/cm2. This is the lowest recorded EOT employing hafnia and TiN electrodes that are compatible with CMOS, and it has important implications for future dynamic random access memory (DRAM) technology.

Miniaturized pH‐Sensitive Field‐Effect Capacitors with Ultrathin Ta2O5 Films Prepared by Atomic Layer Deposition

Miniaturized electrolyte–insulator–semiconductor capacitors (EISCAPs) with ultrathin gate insulators have been studied in terms of their pH‐sensitive sensor characteristics: three different EISCAP systems consisting of Al–p‐Si–Ta2O5(5 nm), Al–p‐Si–Si3N4(1 or 2 nm)–Ta2O5 (5 nm), and Al–p‐Si–SiO2(3.6 nm)–Ta2O5(5 nm) layer structures are characterized in buffer solution with different pH values by means of capacitance–voltage and constant capacitance method. The SiO2 and Si3N4 gate insulators are deposited by rapid thermal oxidation and rapid thermal nitridation, respectively, whereas the Ta2O5 film is prepared by atomic layer deposition. All EISCAP systems have a clear pH response, favoring the stacked gate insulators SiO2–Ta2O5 when considering the overall sensor characteristics, while the Si3N4(1 nm)–Ta2O5 stack delivers the largest accumulation capacitance (due to the lower equivalent oxide thickness) and a higher steepness in the slope of the capacitance–voltage curve among the studied stacked gate insulator systems.

Group IV Transition Metal (M = Zr, Hf) Precursors for High-κ Metal Oxide Thin Films.

This paper describes the synthesis of eight novel zirconium and hafnium complexes containing N-alkoxy carboxamidate-type ligands, as potential precursors for metal oxides and atomic layer deposition (ALD) for HfO2. A series of ligands, viz., N-ethoxy-2,2-dimethylpropanamide (edpaH), N-ethoxy-2-methylpropanamide (empaH), and N-methoxy-2,2-dimethylpropanamide (mdpaH), were used to afford complexes Zr(edpa)4 (1), Hf(edpa)4 (2), Zr(empa)4 (3), Hf(empa)4 (4), Zr(mdpa)4 (5), Hf(mdpa)4 (6), ZrCp(edpa)3 (7), and HfCp(edpa)3 (8). Thermogravimetric analysis curves assessed for the evaporation characteristics of complexes 1-8 revealed single-step weight losses with low residues, except for the mdpa-containing complexes. Single-crystal X-ray diffraction studies of 1, 2, 5, and 6 revealed that all the complexes have monomeric molecular structures, with the central metal ion surrounded by eight oxygen atoms from the four bidentate alkoxyalkoxide ligands. Among the complexes prepared, 8 exhibited a low melting point (64 °C), good volatility (1 Torr at 112 °C), high thermal stability, and excellent endurance over 6 weeks at 120 °C. Therefore, an ALD process for the growth of HfO2 was developed using HfCp(edpa)3 (8) as a novel precursor. Furthermore, the HfO2 film exhibited a low capacitance equivalent oxide thickness of ∼1.5 nm, with Jg as low as ∼3 × 10-4 A/cm2 at Vg -1 V in a metal-insulator-semiconductor capacitor (Au/HfO2/p-Si).

Effects of pre- and post-microwave annealing treatments on pGe MOS device

Effects of pre- and post- microwave annealing (MWA) treatment on electrical characteristics of p-type Ge substrate (pGe) metal-oxide-semiconductor (MOS) devices were investigated in this work. The physical mechanism was studied with an X-ray photoelectron spectroscopy analysis. The pre-MWA treatment, which is similar to conventional post oxidation annealing on interfacial layer (IL), can passivate the oxygen vacancy by chemisorbed oxygen. The excess chemisorbed oxygen atoms may be left at the interface between IL and high-k, which would induce more interface/oxide traps and form more unstable components in IL. The chemisorbed oxygen can be replaced with well-bonded oxygen by using a post-MWA treatment on high-k dielectric , instead of a conventional post deposition annealing. As a result, pGe MOS device with a double-MWA treatment exhibits low equivalent oxide thickness value (~0.65 nm), small frequency dispersion, low interface trap density, and excellent reliability characteristics without increasing the leakage current. The oxygen vacancy passivation and chemisorbed oxygen suppression with a double-MWA treatment are crucial for high performance Ge MOS device and monolithic 3D IC applications. • The effect of pre- and post- microwave annealing (MWA) treatment is compared. • Oxygen vacancy can be passivated by chemisorbed oxygen in pre MWA. • Excess chemisorbed oxygen can be replaced with well-bonded oxygen by post MWA. • A p-type Ge substrate capacitor can be improved by double MWA.

Identification of two-dimensional layered dielectrics from first principles

To realize effective van der Waals (vdW) transistors, vdW dielectrics are needed in addition to vdW channel materials. We study the dielectric properties of 32 exfoliable vdW materials using first principles methods. We calculate the static and optical dielectric constants and discover a large out-of-plane permittivity in GeClF, PbClF, LaOBr, and LaOCl, while the in-plane permittivity is high in BiOCl, PbClF, and TlF. To assess their potential as gate dielectrics, we calculate the band gap and electron affinity, and estimate the leakage current through the candidate dielectrics. We discover six monolayer dielectrics that promise to outperform bulk HfO2: HoOI, LaOBr, LaOCl, LaOI, SrI2, and YOBr with low leakage current and low equivalent oxide thickness. Of these, LaOBr and LaOCl are the most promising and our findings motivate the growth and exfoliation of rare-earth oxyhalides for their use as vdW dielectrics.

Notable difference between rapid-thermal and microwave annealing on Ge pMOSFETs

Effects of rapid-thermal-annealing (RTA) and microwave annealing (MWA) on Ge pMOSFET with GeOx interfacial layer (IL) and HfO2 gate dielectric were studied in this work. High gate leakage and low hole mobility may be induced by the diffusion of GeOx during RTA thermal process. A high hole mobility of ~510 cm2/V-s, low equivalent oxide thickness (EOT) of ~0.7 nm, and very low gate leakage density of ~10−4 A/cm2 at V = VFB + 1 V in Ge pMOSFET can be simultaneously achieved with the efficient annealing effects of MWA on hydrogen plasma (H*) treated GeOx IL due to the suppression of GeOx out-diffusion. The notable difference between RTA and MWA can be attributed to good annealing effects on gate stack by using a MWA with low effective thermal budget.

Enhancement of electrical performance of Ge-based metal-oxide-semiconductor capacitor via formation of trigonal-Sm2O3

In this study, Sm2O3/Ge stack based capacitor prepared from thermally oxidized/nitrided sputtered metallic Sm on Ge semiconductor in N2O ambient for several oxidation/nitridation durations, i.e., 5 – 20 min have been comprehensively investigated. The film crystallinity, chemical composition and interface chemical bonding states stability was characterized from X-ray diffraction (XRD), Raman spectroscopy and X-ray photoelectron spectroscopy (XPS). Formation of trigonal-Sm2O3 dielectric interface together with an interfacial layer containing asymmetrically distributed (GeO, SmOGe and GeN) species has been verified. Suppression of GeO (g) volatilization was evident from the XPS analysis due to germanate (SmOGe) formation. Structural morphology characterization using high resolution transmission electron microscope (HRTEM) also validated double stack amorphous interfaces obtaining physical oxide thickness (tox) from 4.25 − 6.91 nm. Band alignment and electrical measurements revealed that oxidation/nitridation duration of 15 min exhibited highest conduction band offset (CBO), ΔEc of 2.60 eV and valence band offset (VBO) ΔEv of 2.98 eV leading to lowest leakage current density Jg∼ 8.38 × 10−6 A cm−2 at enhanced breakdown field, EBD of 13.31 MV cm−1. The large breakdown field has been ascribed to fewest effective oxide charge (Qeff), slow trap density, (Qit) and interface traps density Dit at this duration. Additionally, a low equivalent oxide thickness, tEOT∼ 0.75 nm with a high dielectric constant k∼ 31.19 eV was achieved but with a price of high Dit∼ 1013 eV−1cm−2. These properties render that Sm2O3 could serve as dielectric material for future high-k/Ge stack based metal oxide semiconductor technology, although requires further investigation for Dit improvement.

Enhanced Electrical Characteristics of Ge nMOSFET by Supercritical Fluid CO2 Treatment With H2O2Cosolvent

Significant improvements on Ge nMOSFET can be achieved by a novel low temperature supercritical phase fluid treatment with H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> cosolvent. Thanks to the reduction of oxygen vacancy and unstable oxidation states, devices with the proposed treatment exhibit a low equivalent oxide thickness of 0.67 nm, 2-order reduction on gate leakage current, 7 times improvement on on-current, very low subthreshold swing of 79 mV/dev, high on/off current ratio, small hysteresis of 43.3 mV, low interface trap density, excellent uniformity and reliability characteristics.

Pseudo Split Gate In0.53Ga0.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis

AbstractIn this work, we present the design and simulation of a novel structure of In0.53Ga0.43As/InP based hetero junction tunnel field effect transistor (HTFET). The proposed HTFET employs two gates: the conventional main gate and a pseudo split gate (PSG) at the drain side. The PSG is placed at the top of the drain region with the same equivalent oxide thickness (EOT) and work function as that of the main gate at an optimized separation from gate electrode. The PSG is not an active gate and it is not connected to either VDD or gate voltage. Two dimensional simulation study has revealed that the proposed device suppresses ambipolar current by ~10 orders of magnitude as compared to a HTFET without overlap and by &gt;7 orders as compared to overlapping gate on drain HTFET (OGD‐HTFET). The PSG‐based HTFET (PSG‐HTFET) also exhibits lesser total gate capacitance as compared to OGD TFET. The proposed PSG‐HTFET offers much better ambipolar suppression even at higher drain doping and lower EOT, as compared to OGD‐HTFET. Further, the PSG‐HTFET exhibits 50% and 40% lesser fall and rise propagation delays respectively as compared to the OGD‐HTEFT. Further, the voltage overshoot and undershoot have also been suppressed in the proposed PSG‐HTFET. The scalability analysis shows that the PSG‐HTFET has better scalability in terms of ambipolar suppression, total gate capacitance, and propagation delays.

Improved electrical characteristics of Ge nMOSFET with suitable nitrogen content in starting interfacial layer

The realization of Ge n-channel MOSFETs (nMOSFET) encounters many challenges, such as poorer interface quality and thermal stability, in comparison with Ge p-channel MOSFETs. Since the oxygen vacancy and interface trap in gate dielectric can be effectively passivated by a nitrogen incorporation, a germanium oxynitride (GeON) starting interfacial layer with suitable nitrogen content was proposed to improve the interface quality of Ge nMOSFETs in this work. A low equivalent oxide thickness of ~0.6 nm, a low gate leakage current of ~6 × 10−4 A/cm2, and a low subthreshold swing of ~120 mV/dec in Ge nMOSFET can be simultaneously achieved by incorporating a nitrogen content of ~20.4% in the GeON starting interfacial layer.

High-k HfxZr1-xO₂ Ferroelectric Insulator by Utilizing High Pressure Anneal

In this article, we report the fabrication of Zr-rich high-k ferroelectric hafnium zirconium oxide (HZO) capacitor with TiN as the top and bottom electrodes demonstrating an equivalent oxide thickness (EOT) of 5.7 Å and remanent polarization (Pr) of ~16 μC/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . High-k-value and low EOT was achieved by utilizing multiphase region of HZO as well as high pressure post metallization annealing (HPPMA). Despite the high-k value of Zr-rich HZO films, the emergence of multiphase region at higher physical-thickness when annealed using rapid thermal annealing (RTA) limits its EOT value. On the contrary, multiphase emerges at a smaller physical thickness in HPPMA due to the formation of more o-phase as revealed by grazing incidence X-ray diffractometer (GIXRD). The smaller physical thickness of HPPMA together with the demonstration of significantly higher dielectric constant (>50) by HZO in the vicinity of multiphase, was therefore, found to be very effective in reducing the EOT.

Low EOT and oxide traps for p-substrate Ge MOS device with hafnium nitride interfacial layer

Effects of interfacial layer on p-substrate germanium (pGe) metal oxide semiconductor (MOS) device were studied in this work. Although excellent characteristics in n-substrate Ge MOS device were reported, pGe MOS device often suffers a poor interface quality and large gate leakage current, while the equivalent oxide thickness (EOT) is scaled down below 1 nm. A novel hafnium nitride (HfN) interfacial layer (IL) is proposed to replace the traditional germanium dioxide thanks to its good thermal stability. As a result, the pGe MOS device with HfN IL exhibits a low EOT of 0.58 nm, a low leakage current density of 2.4 × 10−4 A/cm2, a lower hysteresis value of 150 mV, a better frequency dispersion, and lower oxide/border traps. Therefore, HfN is a promising IL to achieve high performance pGe MOS device.

Low Equivalent Oxide Thickness and Leakage Current of pGe MOS Device by Removing Low Oxidation State in GeOx With H2 Plasma Treatment

A low equivalent-oxide-thickness of 0.58 nm and a low gate leakage current density of $\sim 2\times 10^{-{5}}$ A/cm2 at VG = VFB – 1 V in p-substrate Ge (pGe) MOS device can be simultaneously achieved by a hydrogen plasma (H*) treatment on GeO2 interfacial layer (IL). It is found that the removal of GeOx with low oxidation state in GeO2 IL play crucial roles on electrical characteristics of pGe MOS device. Through a H* treatment, the electrical and reliability characteristics are improved by a GeO2 IL with high oxidation state. Therefore, a GeO2 IL with H* treatment is promising for high performance pGe MOS devices.

Effects of post deposition annealing atmosphere on interfacial and electrical properties of HfO2/Ge3N4 gate stacks

Effects of post deposition annealing (PDA) atmosphere, including oxygen (O2) gas and forming gas (FG), on interfacial and electrical properties of a HfO2 gate dielectric on nitrided Ge are analyzed. Experiments to study the dielectric morphology, interface quality, and chemical composition of HfO2/Ge3N4/Ge devices were carried out using X-ray diffraction, high-resolution transmission electron microscopy (HRTEM) imaging, and X-ray photoelectron spectroscopy (XPS) measurements, respectively. The XPS study confirmed that O2 PDA effectively improves the HfO2 film stoichiometry, and the stability of the interface between HfO2/Ge3N4/Ge stacks is enhanced. Further, HRTEM images showed that the interface between HfO2/Ge3N4/Ge stacks for O2-annealed devices was smooth, uniform, and flat. The experimental results for devices annealed in O2 at 500 °C exhibited improved interfacial and electrical characteristics, such as a high dielectric constant of ~19.50; high capacitance, 1.24 nF, low equivalent oxide thickness, 1.74 nm; interface trap density, 2.18 × 1011 cm−2 eV−1; oxide charges, 2.50 × 1012 cm−2; and gate leakage currents in the order nA of 0.5 × 10−9 A/cm2, as compared with FG annealing devices. The Fowler−Nordheim tunneling current conduction mechanism was also verified. Therefore, these results are evidence that the O2 PDA process improves the interfacial and electrical properties of HfO2/Ge3N4/Ge metal-oxide-semiconductor (MOS) devices as compared with FG annealing, which is important for future Ge-based complementary MOS device performance and reliability.