Low-end Devices Research Articles

PDAC-SL: A PUF-enabled drone access control technique for smart logistics

The conventional logistics’ paradigm is being replaced with smarter ways of supply chain management to readily serve the customers with quick modes of delivery in affordable operational costs. The weak infrastructure in rural terrain and congested roads in urban cities act as a big impediment in the successful accomplishment of last mile delivery down the lane across the complete chain of logistics. The traditional logistics has been evolved and improved in many respects, the last mile delivery is still plagued by security and privacy risks in logistics. The use of drones for package deliveries may offer promising gains in terms of efficiency. Nonetheless, drones undergo security and privacy risks besides physical threats for being deployed in public places communicating on open channels. Thus, more efforts are needed to secure the communication of inducted drones in delivery assignments. We propose a novel PUF-enabled drone access control mechanism PDAC-SL for smart logistics. By the careful employment of symmetric crypto-primitives, the contributed protocol not only supports low end devices but stands resistant to physical drone and other known threats besides preserving anonymity and untraceability features. The RoR model-based formal security analysis and performance analysis demonstrate distinct security properties and applicability of the PDAC-SL.

PCB Defect Detection Based on Improved Deep Learning Model

Printed circuit boards (PCBs) play a critical role in electronic products. Ensuring these products’ long-term reliability and consistent performance requires effective PCB defect detection. Although existing deep learning models for PCB defect detection are not highly accurate, they often neglect capability considerations. This paper introduces a precise, fast, and lightweight defect detection model, CCG-YOLO, based on an enhanced YOLOv5 model to address this issue. The enhancements in CCG-YOLO can be summarized as follows: (1) Improved Backbone network: The feature extraction ability of the Backbone network is enhanced by introducing a C3HB module, which fosters spatial interaction capabilities. (2) Lightweight feature fusion network: A lightweight convolution structure called Ghost-Shuffle Convolution is incorporated in the feature fusion network, remarkably reducing model parameters while maintaining performance. (3) Efficient residual networking: To enhance model performance further, a CNeB module is introduced based on the ConvNeXt network, which replaces the C3 module in the Neck. CNeB improves model detection accuracy and reduces the number of model parameters. The combination of these enhancements results in impressive performance. CCG-YOLO achieves mean average precision (mAP@0.5) of 99.5% and 88.75% in mAP@0.5:0.95 on the TDD-Net public dataset. Compared with the original YOLOv5s algorithm, CCG-YOLO offers a 4.24% improvement in mAP@0.5:0.95, a 1[Formula: see text]MB reduction in model size, a 0.472[Formula: see text]M decrease in the number of parameters, a 0.6G floating point operation reduction in computational complexity, and a 120 frames per second real-time inference speed. These experimental results underscore that the proposed model excels in accuracy and speed and has a compact size for PCB defect detection. Moreover, CCG-YOLO is easily deployable on low-end devices, making it well-suited for meeting the real-time requirements of industrial defect detection.

Experimental evaluation of interactive Edge/Cloud Virtual Reality gaming over Wi-Fi using unity render streaming

Virtual Reality (VR) streaming enables end-users to seamlessly immerse themselves in interactive virtual environments using even low-end devices. However, the quality of the VR experience heavily relies on Wireless Fidelity (Wi-Fi) performance, since it serves as the last hop in the network chain. Our study delves into the intricate interplay between Wi-Fi and VR traffic, drawing upon empirical data and leveraging a Wi-Fi simulator. In this work, we further evaluate Wi-Fi’s suitability for VR streaming in terms of the Quality of Service (QoS) it provides. In particular, we employ Unity Render Streaming to remotely stream real-time VR gaming content over Wi-Fi 6 using Web Real-Time Communication (WebRTC), considering a server physically located at the network’s edge, near the end user. Our findings demonstrate the system’s sustained network performance, showcasing minimal round-trip time (RTT) and jitter at 60 and 90 frames per second (fps). In addition, we uncover the characteristics and patterns of the generated traffic streams, unveiling a distinctive video transmission approach inherent to WebRTC-based services: the systematic packetization of video frames (VFs) and their transmission in discrete batches at regular intervals, regardless of the targeted frame rate. This interval-based transmission strategy maintains consistent video packet delays across video frame rates but leads to increased Wi-Fi airtime consumption. Our results demonstrate that shortening the interval between batches is advantageous, as it enhances Wi-Fi efficiency and reduces delays in delivering complete frames.

Augmented reality, virtual reality, and mixed reality: A pragmatic view from diffusion of innovation

This research offers a pragmatic view on the adoption of Augmented Reality (AR), Virtual Reality (VR), and Mixed Reality (MR) in designing the built environment. Participants from 20 U.S. states and beyond formed a non-probability sample representing small to mid-sized Architecture, Engineering, and Construction (AEC) firms. The author engaged 59 professional participants through a 26-question online questionnaire, informed by existing literature and reviewed by two industry experts. Three additional expert participants provided comprehensive insights via semi-structured interviews. Results highlight design visualization and client presentations as top AR, VR, and MR applications. Key benefits include improved design assessment, early error detection, and heightened client satisfaction. Design collaboration was less prominent than suggested by the literature. Notable challenges persist in first-time user adoption and cost factors of equipment and training. Thus, the cost-benefit balance drives the dominance of older, lower-end devices found in this study despite the availability of advanced, high-fidelity infrastructure.

PARSECS_RT: A real-time PARSECS-based communication protocol stack for critical sensing applications

The real-time characteristics of modular systems have been a long sought-after goal in many industries including automotive, aeronautics or mobile robotics. Yet scientists and practitioners are still struggling to find widespread implementation solutions that may accommodate diverse inter-modular real-time communication requirements. In an attempt to cover this research gap, the current paper proposes a real-time version of the PARSECS protocol for low-end devices. Our new protocol, coined as PARSECS_RT, was designed according to Open Systems Interconnection Reference Model. It offers a full communication stack from the physical layer to the application layer on top of the SPI interface in order to provide a stable, hard real-time communication platform. PARSECS_RT was evaluated in real and simulated environments providing promising results.

A Practical Approach for Employing Tensor Train Decomposition in Edge Devices

Deep Neural Networks (DNN) have made significant advances in various fields including speech recognition and image processing. Typically, modern DNNs are both compute and memory intensive, therefore their deployment in low-end devices is a challenging task. A well-known technique to address this problem is Low-Rank Factorization (LRF), where a weight tensor is approximated by one or more lower-rank tensors, reducing both the memory size and the number of executed tensor operations. However, the employment of LRF is a multi-parametric optimization process involving a huge design space where different design points represent different solutions trading-off the number of FLOPs, the memory size, and the prediction accuracy of the DNN models. As a result, extracting an efficient solution is a complex and time-consuming process. In this work, a new methodology is presented that formulates the LRF problem as a (FLOPs vs. memory vs. prediction accuracy) Design Space Exploration (DSE) problem. Then, the DSE space is drastically pruned by removing inefficient solutions. Our experimental results prove that the design space can be efficiently pruned, therefore extract only a limited set of solutions with improved accuracy, memory, and FLOPs compared to the original (non-factorized) model. Our methodology has been developed as a stand-alone, parameterized module integrated into T3F library of TensorFlow 2.X.

Efficient Placement of Decomposable Aggregation Functions for Stream Processing over Large Geo-Distributed Topologies

A recent trend in stream processing is offloading the computation of decomposable aggregation functions (DAF) from cloud nodes to geo-distributed fog/edge devices to decrease latency and improve energy efficiency. However, deploying DAFs on low-end devices is challenging due to their volatility and limited resources. Additionally, in geo-distributed fog/edge environments, creating new operator instances on demand and replicating operators ubiquitously is restricted, posing challenges for achieving load balancing without overloading devices. Existing work predominantly focuses on cloud environments, overlooking DAF operator placement in resource-constrained and unreliable geo-distributed settings. This paper presents NEMO, a resource-aware optimization approach that determines the replication factor and placement of DAF operators in resource-constrained geo-distributed topologies. Leveraging Euclidean embeddings of network topologies and a set of heuristics, NEMO scales to millions of nodes and handles topo-logical changes through adaptive re-placement and re-replication decisions. Compared to existing solutions, NEMO achieves up to 6× lower latency and up to 15× reduction in communication cost, while preventing overloaded nodes. Moreover, NEMO re-optimizes placements in constant time, regardless of the topology size. As a result, it lays the foundation to efficiently process continuous data streams on large, heterogeneous, and geo-distributed topologies.

FL-ToLeD: An Improved Lightweight Attention Convolutional Neural Network Model for Tomato Leaf Diseases Classification for Low-end Devices

FL-ToLeD: An Improved Lightweight Attention Convolutional Neural Network Model for Tomato Leaf Diseases Classification for Low-end Devices

ChamelIoT: a tightly- and loosely-coupled hardware-assisted OS framework for low-end IoT devices

The evergrowing Internet of Things (IoT) ecosystem continues to impose new requirements and constraints on every device. At the edge, low-end devices are getting pressured by increasing workloads and stricter timing deadlines while simultaneously are desired to minimize their power consumption, form factor, and memory footprint. Field-Programmable Gate Arrays (FPGAs) emerge as a possible solution for the increasing demands of the IoT. Reconfigurable IoT platforms enable the offloading of software tasks to hardware, enhancing their performance and determinism. This paper presents ChamelIoT, an agnostic hardware operating systems (OSes) framework for reconfigurable IoT devices. The framework provides hardware acceleration for kernel services of different IoT OSes by leveraging the RISC-V open-source instruction set architecture (ISA). The ChamelIoT hardware accelerator can be deployed in a tightly- or loosely-coupled approach and implements the following kernel services: thread management, scheduling, synchronization mechanisms, and inter-process communication (IPC). ChamelIoT allows developers to run unmodified applications of three well-established OSes, RIOT, Zephyr, and FreeRTOS. The experiments conducted on both coupling approaches consisted of microbenchmarks to measure the API latency, the Thread Metric benchmark suite to evaluated the system performance, and tests to the FPGA resource consumption. The results show that the latency can be reduced up to 92.65% and 89.14% for the tightly- and loosely-coupled approaches, respectively, the jitter removed, and the execution performance increased by 199.49% and 184.85% for both approaches.

Security Framework for IoT Implementing Random Forest Classifier

The Internet of Things will become commonplace by making global connections possible at any moment. The necessity of well-thought-out, carefully implemented, and strictly enforced security standards over the entire lifecycle of IoT devices cannot be overstated.The Internet of Things (IoT) is a relatively new phenomenon that connects disparate computing infrastructures and infrastructure components. Given that the vast majority of the data collected will be shared with an unknowable audience, security is of paramount importance when connecting multiple independent IoT units across the Internet. This article provides a comprehensive review of the state of security in the Internet of Things.The essay emphasizes the necessity to provide security in the device itself alongside conventional security solutions to offer a method employing machine learning exible for preventing, detecting, diagnosing, isolating, and counteracting successful breaches.The bulk of IoT end hosts are low-end devices, This means that many common security practices cannot be used to protect IoTdevices., leaving IoT services and the wider Internet vulnerable to attacks and exploits.To solve this problem, this article presents a unified IoT framework that employs machine learning to implementthe proposed GNRS&NC architecture. This framework's primary goal is to ensure the safety of IoT devices.The framework makes use of random forest classifier. The suggested architecture allows for the seamless incorporation of regional IoT infrastructures into global frameworks without compromising on usability, interoperability, or security.

Software-Based Security Approach for Networked Embedded Devices

As the Internet of Things (IoT) continues to expand, data security has become increasingly important for ensuring privacy and safety, especially given the sensitive and, sometimes, critical nature of the data handled by IoT devices. There exist hardware-based trusted execution environments used to protect data, but they are not compatible with low-cost devices that lack hardware-assisted security features. The research in this paper presents software-based protection and encryption mechanisms explicitly designed for embedded devices. The proposed architecture consists of two parts: the Agent, which is designed to work with low-cost, low-end devices without requiring modifications to the underlying hardware, and the Computing Module, which is designed for slightly more computationally powerful devices. The Computing Module enables devices to write data in protected memory and continuously verifies its integrity to provide protection. Additionally, it utilizes the Agents located on the device to safeguard device applications against attacks by requesting the Agent to generate an application code signature and validating it. The proposed solution is an alternative data security approach for low-cost IoT devices without compromising performance or functionality. Our work underscores the importance of developing secure and cost-effective solutions for protecting data in the context of IoT.

A Multi-Agent Prediction Method for Data Sampling and Transmission Reduction in Internet of Things Sensor Networks.

Sensor networks can provide valuable real-time data for various IoT applications. However, the amount of sensed and transmitted data should be kept at a low level due to the limitations imposed by network bandwidth, data storage, processing capabilities, and finite energy resources. In this paper, a new method is introduced that uses the predicted intervals of possible sensor readings to efficiently suppress unnecessary transmissions and decrease the amount of data samples collected by a sensor node. In the proposed method, the intervals of possible sensor readings are determined with a multi-agent system, where each agent independently explores a historical dataset and evaluates the similarity between past and current sensor readings to make predictions. Based on the predicted intervals, it is determined whether the real sensed data can be useful for a given IoT application and when the next data sample should be transmitted. The prediction algorithm is executed by the IoT gateway or in the cloud. The presented method is applicable to IoT sensor networks that utilize low-end devices with limited processing power, memory, and energy resources. During the experiments, the advantages of the introduced method were demonstrated by considering the criteria of prediction interval width, coverage probability, and transmission reduction. The experimental results confirm that the introduced method improves the accuracy of prediction intervals and achieves a higher rate of transmission reduction compared with state-of-the-art prediction methods.

A Research to Improve Contiguous Memory Allocation in Linux Kernel

The demand for Contiguous Memory Allocation (CMA) has witnessed significant growth in both low-end and high-end devices in recent years. However, the existing practices for utilizing CMA prove insufficient, particularly when catering to the needs of low-end (32-bit) devices. CMA, a Linux program used for memory reservation and allocation, faces limitations in its current implementations. Presently, techniques such as Scatter-Gather Direct Memory Access (DMA), Input Output Memory Management Unit (IOMMU), and Memory Reservation are commonly employed for contiguous memory allocation. Unfortunately, these methods are financially impractical for low-end devices and struggle to efficiently allocate substantial memory chunks, leading to latency concerns. In this paper, we introduce an improved CMA approach that intelligently allocates virtual memory for data mapping as needed. Alternatively, it directly allocates and deallocates physical memory without the necessity of virtual memory mapping, employing the DMA_KERNEL_NO_MAPPING attribute within the DMA Application Programming Interface (API). By adopting this method, latency is reduced, and the facilitation of larger memory allocations is promoted, addressing the limitations of the current techniques.

Optimizing Immersion: Analyzing Graphics and Performance Considerations in Unity3D VR Development

Aims: Virtual reality (VR) is a new approach that gives users an immersive experience. VR applications frequently experience performance bottlenecks due to the high processing cost of displaying real-time animations multiple times (for both eyes) and the limited resources of wearable devices, performance optimization serves a significant part in VR application development. The goal of this paper is to investigate approaches and techniques available in Unity3D to improve the immersion of VR in virtual reality. This entails studying visuals and performance elements to design more fluid and engaging VR apps.
 Study Design: Quantitative analysis.
 Methodology: Systematic literature reviews, Consensus on the design space for VR-based education would greatly benefit future advances. To do this, we use a systematic mapping technique to the literature, extracting essential data from papers indexed in four academic online databases.
 Results: VR applications include extra aspects like graphics rendering and actual time animation, performance improvements for VR apps might differ significantly from those for standard software. Fully immersive virtual environments vary from standard virtual reality environments in that they can record entire body movements. This skill enables users to engage with other avatars, computer-controlled entities, and artifacts in the virtual world using their complete range of physical activities. VR performance optimization, in essence, relates to the methods, tactics, and procedures used to ensure that VR experiences function as smoothly as feasible.
 Conclusion: This optimization might be performed on different kinds of technology, particularly low-end devices, without sacrificing visual fidelity or immersive experience. VR is well-known for. It is critical to optimize visuals as well as performance in Unity3D VR apps to produce immersive and engaging experiences. Balancing great aesthetics with seamless performance necessitates a thorough grasp of Unity's features as well as a dedication to constant optimization.

WheatLFANet: in-field detection and counting of wheat heads with high-real-time global regression network

BackgroundDetection and counting of wheat heads are of crucial importance in the field of plant science, as they can be used for crop field management, yield prediction, and phenotype analysis. With the widespread application of computer vision technology in plant science, monitoring of automated high-throughput plant phenotyping platforms has become possible. Currently, many innovative methods and new technologies have been proposed that have made significant progress in the accuracy and robustness of wheat head recognition. Nevertheless, these methods are often built on high-performance computing devices and lack practicality. In resource-limited situations, these methods may not be effectively applied and deployed, thereby failing to meet the needs of practical applications.ResultsIn our recent research on maize tassels, we proposed TasselLFANet, the most advanced neural network for detecting and counting maize tassels. Building on this work, we have now developed a high-real-time lightweight neural network called WheatLFANet for wheat head detection. WheatLFANet features a more compact encoder-decoder structure and an effective multi-dimensional information mapping fusion strategy, allowing it to run efficiently on low-end devices while maintaining high accuracy and practicality. According to the evaluation report on the global wheat head detection dataset, WheatLFANet outperforms other state-of-the-art methods with an average precision AP of 0.900 and an R2 value of 0.949 between predicted values and ground truth values. Moreover, it runs significantly faster than all other methods by an order of magnitude (TasselLFANet: FPS: 61).ConclusionsExtensive experiments have shown that WheatLFANet exhibits better generalization ability than other state-of-the-art methods, and achieved a speed increase of an order of magnitude while maintaining accuracy. The success of this study demonstrates the feasibility of achieving real-time, lightweight detection of wheat heads on low-end devices, and also indicates the usefulness of simple yet powerful neural network designs.

A Review of YOLO Object Detection Model in Forensic Evidence Analysis

The rate of crimes is an ever-increasing problem in our society. A huge number of cases are still pending and need to be solved. Collecting and analysing evidence is becoming a more important complex task. And it is becoming brain storming thing for officers. With the availability of enormous data and the need for computer vision systems, research on object detection models/algorithms has become crucial over the last few decades. With various CNN architectures available, the state- of-the-art You Look Only Once (YOLO) model is very popular for many reasons mainly fast detection even on low-end devices. Followed by introduction and background this paper reviews the innovative and descriptive approach YOLO takes at object detection and how it is helpful in Forensic Evidence Detection and Analysis. Key Words: YOLO, Forensic Evidence, Object Detection, Crime Scene

PReFeR : P hysically Re lated F unction bas e d R emote Attestation Protocol

Remote attestation is a request-response based security service that permits a trusted entity (verifier) to check the current state of an untrusted remote device (prover). The verifier initiates the attestation process by sending an attestation challenge to the prover; the prover responds with its current state, which establishes its trustworthiness. Physically Unclonable Function (PUF) offers an attractive choice for hybrid attestation schemes owing to its low overhead security guarantees. However, this comes with the limitation of secure storage of the PUF model or large challenge-response database on the verifier end. To address these issues, in this work, we propose a hybrid attestation framework, named PReFeR , that leverages a new class of hardware primitive known as Physically Related Function (PReF) to remotely attest low-end devices without the requirement of secure storage or heavy cryptographic operations. It comprises a static attestation scheme that validates the memory state of the remote device prior to code execution, followed by a dynamic run-time attestation scheme that asserts the correct code execution by evaluating the content of special registers present in embedded systems, known as hardware performance counters (HPC). The use of HPCs in the dynamic attestation scheme mitigates the popular class of attack known as the time-of-check-time-of-use (TOCTOU) attack, which has broken several state-of-the-art hybrid attestation schemes. We demonstrate our protocol and present our experimental results using a prototype implementation on Digilent Cora Z7 board, a low-cost embedded platform, specially designed for IoT applications.

A Circuit-Level Solution for Secure Temperature Sensor

Temperature sensors play an important role in modern monitoring and control applications. When more and more sensors are integrated into internet-connected systems, the integrity and security of sensors become a concern and cannot be ignored anymore. As sensors are typically low-end devices, there is no built-in defense mechanism in sensors. It is common that system-level defense provides protection against security threats on sensors. Unfortunately, high-level countermeasures do not differentiate the root of cause and treat all anomalies with system-level recovery processes, resulting in high-cost overhead on delay and power consumption. In this work, we propose a secure architecture for temperature sensors with a transducer and a signal conditioning unit. The proposed architecture estimates the sensor data with statistical analysis and generates a residual signal for anomaly detection at the signal conditioning unit. Moreover, complementary current–temperature characteristics are exploited to generate a constant current reference for attack detection at the transducer level. Anomaly detection at the signal conditioning unit and attack detection at the transducer unit make the temperature sensor attack resilient to intentional and unintentional attacks. Simulation results show that our sensor is capable of detecting an under-powering attack and analog Trojan from a significant signal vibration in the constant current reference. Furthermore, the anomaly detection unit detects anomalies at the signal conditioning level from the generated residual signal. The proposed detection system is resilient against any intentional and unintentional attacks, with a detection rate of 97.73%.

Wi-Fi frame detection via spiking neural networks with memristive synapses

With increasing performance of deep learning, researchers have employed Deep Neural Networks (DNNs) for wireless communications. In particular, mechanisms for detecting Wi-Fi frames that use DNNs demonstrate their excellent performances in terms of detection accuracy. However, DNNs require significant amount of computation resources. Thus, if the DNN-based mechanisms are used in mobile devices or low-end devices, their battery would be quickly depleted. Spiking Neural Networks (SNNs), which are regarded as the next generation of neural network, have advantages over DNNs: low energy consumption and limited computational complexity. Motivated by these advantages, in this paper, we propose a mechanism to detect a Wi-Fi frame using SNNs and show the feasibility of SNNs for Wi-Fi detection. The mechanism is composed of a preprocessing module for converting collected signals and an SNN module for detecting Wi-Fi frames. The SNN module employs Leaky Integrate-and-Fire (LIF) neurons and Spike-Timing-Dependent Plasticity (STDP) learning rule. To reflect the features of an actual neuromorphic hardware system, our SNN module considers memristive synaptic features such as non-linear weight updates. Our experimental study demonstrates the detection capabilities of the proposed mechanism are comparable to those of previous mechanisms that use DNNs, CNNs and RNNs while consuming definitely less energy than the previous mechanism.

A lightweight remote attestation using PUFs and hash-based signatures for low-end IoT devices

Remote attestation is a powerful mechanism that allows a verifier to know if the hardware of an IoT (Internet-of-Thing) device (acting as a prover) has been counterfeited or tampered with and if its firmware has been altered. Remote attestation is based on collecting and reporting measurements in a trusted way, and should be lightweight for resource-constrained IoT devices. This work proposes to include a low-cost Root of Trust for Measuring and Reporting (RoTMR) in the prover, based on the combination of a Physically Unclonable Function (PUF) and an Attestation Read-Only Memory (A-ROM), and to use hash-based digital signatures in the attestation protocol. The proposed RoTMR is addressed to IoT devices based on a microcontroller that executes some application code (the measurable object) located in an external non-volatile memory accessible by an attacker. The secret keys required by the digital signatures are not stored but reconstructed using the PUF. The A-ROM contains the attestation instructions and ensures that its contents cannot be altered and that its instructions are executed sequentially without modification. The use of hash-based digital signatures makes the solution quantum-resistant and very robust because its security relies solely on the unidirectionality of a hash function. The proposed attestation protocol takes advantage of the fact that One-Time Signature (OTS) generation and Many-Time Signature (MTS) verification are very well suited for low-end devices, and the MTS scheme is suitable for the verifier application context. The proposal was validated experimentally with the ESP32 microcontroller, which is widely employed in IoT devices, by using its SRAM as PUF and implementing WOTS+, which is a type of Winternitz One-Time Signature scheme (WOTS), the One-Time Signature of Smart Digital Signatures scheme (SDS-OTS), and the MTS schemes constructed with them. The OTS schemes require smaller codes and thus smaller A-ROM than MTS and ECDSA (Elliptic Curve Digital Signature Algorithm). The code of one of the WOTS+ takes about 4 times less space than ECDSA. In terms of execution times, the OTS schemes are very fast. One of the WOTS+ performs all the signature operations in a few tens of milliseconds. The OTS schemes (especially the SDS-OTS) are also very efficient in terms of communication bandwidth because they use small signatures compared to other post-quantum solutions.