Low Network Diameter Research Articles

The CTH Network: An NoC Platform for Scalable and Energy Efficient Application Mapping Solution

Multi-threaded design of the applications has given a new dimension to the execution concurrency. The Network-on-Chip (NoC) infrastructure has evolved as the communication backbone in multiprocessor System-on-Chips (MPSoCs) to exploit Thread-Level Parallelism (TLP). Mapping the threads of various applications on the processing cores is crucial in utilizing the resources of a many-core system. An application's performance depends primarily on the mapping strategy. However, the performance of an application gets influenced significantly by the underlying network architecture of the NoC. The present work proposes a run-time application mapping technique based on the Cube-Tree-Hybrid (CTH) topology focusing on the traffic load balancing across the network. The mapping overhead decreased significantly by exploiting the low network diameter of CTH with its high scalability and path diversity, projecting a 31% reduction in normalized execution time over the prevalent algorithms on the existing mapping platforms. Rigorous experimentation with varying application and network sizes is carried out across mesh, ZMesh, torus, and Mest-of-Tree (MoT) networks. The experimental observations project that the proposed algorithm results in sustainable application performance with 15%-21% gain in the overall energy consumption over the existing state-of-the-art techniques across various benchmark workloads.

Energy and performance improvements in stencil computations on multi-node HPC systems with different network and communication topologies

Energy and performance improvements in stencil computations are relevant for both application developers and data center administrators. They appear as the fundamental scheme in many large-scale scientific simulations and workloads. Many research efforts have focused on some estimation techniques of the energy usage of HPC systems based on specific characteristics of parallel applications. In case of stencils, we have previously concentrated on detailed estimations of energy consumption and the energy-aware distribution of stencil computations on heterogeneous processors. However, we have restricted our comprehensive studies to a single heterogeneous computing node only. In this paper, we show how scheduling and optimization techniques can be applied for energy and performance improvements of stencil computations on multi-node HPC systems using different network topologies. We formulate a scheduling model together with a new Tabu Search algorithm, called Task Movement (TM), taking into account the communication hierarchies, to minimize the overall energy usage and the execution time of stencil computations. Experimental studies show that this algorithm solves the considered problem more efficiently comparing to other, simpler heuristics. We present computational experiments for a reference 7 point stencil computation pattern on three commonly used low-diameter network topologies: Fat-tree, Dragonfly, and Torus. According to our studies, the most promising multi-node HPC architecture for stencil computations is based on the Torus network concept. Finally, we argue that the proposed scheduling model and TM algorithm can be easily adopted within existing high-level parallel execution environments for stencils automatic performance tuning.

Approximate Moore Graphs are good expanders

We revisit the classical question of the relationship between the diameter of a graph and its expansion properties. One direction is well understood: expander graphs exhibit essentially the lowest possible diameter. We focus on the reverse direction, showing that “sufficiently large” graphs of fixed diameter and degree must be “good” expanders. We prove this statement for various definitions of “sufficiently large” (multiplicative/additive factor from the largest possible size), for different forms of expansion (edge, vertex, and spectral expansion), and for both directed and undirected graphs. A recurring theme is that the lower the diameter of the graph and (more importantly) the larger its size, the better the expansion guarantees. Aside from inherent theoretical interest, our motivation stems from the domain of network design. Both low-diameter networks and expanders are prominent approaches to designing high-performance networks in parallel computing, HPC, datacenter networking, and beyond. Our results establish that these two approaches are, in fact, inextricably intertwined. We leave the reader with many intriguing questions for future research.

ACOR: Adaptive congestion-oblivious routing in dragonfly networks

Low-diameter network topologies require non-minimal routing to avoid network congestion, such as Valiant routing. This increases base latency but avoids congestion issues. Optimized restricted variants focus on reducing path length. However, these optimizations only reduce paths for local traffic, where source and destination of each packet belong to the same partition of the network. This paper introduces ACOR: Adaptive Congestion-Oblivious Routing. ACOR leverages the restricted and recomputation mechanisms to reduce path length for local and global traffic, and extends it when the network conditions are adverse. ACOR relies on a sequence of misrouting policies ordered by path length. A hysteresis mechanism improves performance and avoids variability in the results. The ACOR mechanism can be combined with other non-minimal routing mechanism such as Piggyback. Results show that ACOR improves base latency in all cases, up to 28% standalone and up to 25.5% when combined with Piggyback, while requiring a simple implementation.

Does the superior position of countries in co-authorship networks lead to their high citation performance

The objective of this research was to determine the macro-topological structure and the relationship between citation performance and centrality measures of co-authorship social networks of countries in the field of Nuclear Science and Technology from 2008 to 2010. The present study applied the network analysis method in order to visualize co-authorship networks. Hypothesized relationships were tested using the authors of 24,308 documents cited in the Web of Science. Data relevant to citation performance of a country was based on the articles published by the researchers of the country in a three-year period and the citation data of articles were collected two years after their publication. The investigation of co-authorship social network in the field of Nuclear Science and Technology revealed that the countries which are members of a Nuclear Club hold a prominent position in the network and their influence or power in the network is greater than other countries. Having characteristics like short mean path length, low network diameter (less than or equal to 6) and relatively high clustering coefficient, this network is regarded as a Small World Network. The results of testing the research hypotheses indicated that as the value of centrality of countries rise, the citation performance of researchers in that country is also improved. The analysis of variance confirmed the validity of stepwise regression analysis in predicting the citation performance of researchers (F=816.958 and p>0.000) and through three steps, three components including degree centrality, beta centrality and flow betweenness centrality were concluded to have multiple correlation with citation performance of researchers

Head‐of‐line blocking avoidance in Slim Fly networks using deadlock‐free non‐minimal and adaptive routing

SummaryInterconnection network performance is a key issue in HPC systems and datacenters, especially as their number of end nodes grows, to cope with application needs. The network topology and the routing algorithm are important factors for performance and cost. Topologies such as fat‐tree or Dragonfly were proposed to maximize network performance while reducing network resources. One of the most promising topologies is Slim Fly, which offers high network bandwidth assuring low network diameter. However, adversarial traffic and/or congestion situations may degrade Slim Fly's performance dramatically. Non‐minimal routings, such as Valiant or UGAL, can mitigate the former problem while queuing schemes can handle the latter one. In this paper, we proposed a combined mechanism to provide Slim Fly network with both non‐minimal routing and queuing schemes by using several virtual networks to guarantee deadlock freedom. Each virtual network consists of a set of virtual channels to store packets separately according to a mapping policy. This diminishes the interaction among traffic flows, thus reducing head‐of‐line blocking. The results obtained from a simulation‐based evaluation show that our proposal enhances the performance in all the traffic cases, in contrast to other mechanisms whose performance drops in certain scenarios.

3D network-on-chip design for embedded ubiquitous computing systems

A novel 3D NoC topology for embedded ubiquitous computing is proposed.A minimal routing algorithm with path diversity in the 3D NoC Topology is used.A power efficient architecture design for NoC-based embedded ubiquitous computing is introduced. Ubiquitous High-Performance Computing applications, such as cyber-physical systems, sensor networks and virtual reality require the support of terascale embedded systems that can deliver higher performance than current systems. Multi-cores, many-cores and heterogeneous processors are becoming the typical design choices to satisfy these requirements. Inter core communication has been one of the major challenges as it affects the bandwidth and power consumption of the multi-cores processors. Network-on-Chips (NoCs) present a fast and scalable interconnection solution to fulfill the requirements of Ubiquitous High-Performance Computing applications. This paper proposes a novel 3D Network-on-Chip called Octagon for Ubiquitous Computing (OUC) that is designed for Embedded Ubiquitous Computing Systems. OUC provides low network diameter and path diversity. Simulation results show that the proposed topology achieves a significant decrease in latency and an average 21.54% and 12.89% improvement in average throughput under hotspot and uniform traffic pattern respectively.

Complex Network Partitioning Using Label Propagation

We present PuLP (partitioning using label propagation), a parallel and memory-efficient graph partitioning method specifically designed to partition low-diameter networks with skewed degree distributions on shared-memory multicore platforms. Graph partitioning is an important problem in scientific computing because it impacts the execution time and energy efficiency of computations on distributed-memory platforms. Partitioning determines the in-memory layout of a graph, which affects locality, intertask load balance, communication time, and overall memory utilization. A novel feature of our PuLP method is that it optimizes for multiple objective metrics simultaneously, while satisfying multiple partitioning constraints. Using our method, we are able to partition a web crawl with billions of edges on a single compute server in under a minute. For a collection of test graphs, we show that PuLP uses up to $7.8\times$ less memory than state-of-the-art partitioners and is $5.0\times$ faster, on average, than a...

Designing efficient high performance server-centric data center network architecture

Data center network (DCN) architecture is regarded as one of the most important determinants of network performance. As the most typical representatives of DCN architecture designs, the server-centric scheme stands out due to its good performance in various aspects. In this paper, we firstly present the design, implementation and evaluation of SprintNet, a novel server-centric network architecture for data centers. SprintNet achieves high performance in network capacity, fault tolerance, and network latency. SprintNet is also a scalable, yet low-diameter network architecture where the maximum shortest distance between any pair of servers can be limited by no more than four and is independent of the number of layers. The specially designed routing schemes for SprintNet strengthen its merits. However, all of these kind of server-centric architectures still suffer from some critical shortcomings owing to the server’s responsibility of forwarding packets. With regard to these issues, in this paper, we then propose a hardware based approach, named “Forwarding Unit” to provide an effective solution to these drawbacks and improve the efficiency of server-centric architectures. Both theoretical analysis and simulations are conducted to evaluate the overall performance of SprintNet and the Forwarding Unit approach with respect to cost-effectiveness, fault-tolerance, system latency, packet loss ratio, aggregate bottleneck throughput, and average path length. The evaluation results convince the feasibility and good performance of both SprintNet and Forwarding Unit.

Scalable Resource Discovery Architecture for Large Scale MANETs

The study conducted a primary investigation into using the Gray cube structure, clustering and Distributed Hash Tables (DHTs) to build an efficient virtual network backbone for Resource Discovery (RD) tasks in large scale Mobile Ad hoc NET works (MANETs). MANET is an autonomous system of mobile nodes characterized by wireless links. One of the major challenges in MANET is RD protocols responsible for advertising and searching network services. We propose an efficient and scalable RD architecture to meet the challenging requirements of reliable, scalable and power-efficient RD protocol suitable for MANETs with potentially thousands of wireless mobile devices. Our RD is based on virtual network backbone created by dividing the network into several non overlapping localities using multi-hop clustering. In every locality we build a Gray cube with locally adapted dimension. All the Gray cubes are connected through gateways and access points to form virtual backbone used as substrate for DHT operations to distribute, register and locate network resources efficiently. The Gray cube is characterized by low network diameter, low average distance and strong connectivity. We evaluated the proposed RD performance and compared it to some of the well known RD schemes in the literature based on modeling and simulation. The results show the superiority of the proposed RD in terms of delay, load balancing, overloading avoidance, scalability and fault-tolerance.

Complex Cloud Datacenters

The network architecture deployed in a data center is of extreme importance and should provide the data center with the high throughput while keeping overprovisioning at the minimum costs. In order to provide these features new complex network based models have been proposed recently. In this paper we give an overview of the proposed models and their characteristics, advantages and problems. We then propose a new datacenter network model that provides easy subgrouping while preserving high bandwidth and low average path length and network diameter.

A Two-Dimensional Low-Diameter Scalable On-Chip Network for Interconnecting Thousands of Cores

This paper introduces the Spidergon-Donut (SD) on-chip interconnection network for interconnecting 1,000 cores in future MPSoCs and CMPs. Unlike the Spidergon network, the SD network which extends the Spidergon network into the second dimension, significantly reduces the network diameter, well below the popular 2D Mesh and Torus networks for one extra node degree and roughly 25 percent more links. A detailed construction of the SD network and a method to reshuffle the SD network's nodes for layout onto the 2D plane, and simple one-to-one and broadcast routing algorithms for the SD network are presented. The various configurations of the SD network are analyzed and compared including detailed area and delay studies. To interconnect a thousand cores, the paper concludes that a hybrid version of the SD network with smaller SD instances interconnected by a crossbar is a feasible low-diameter network topology for interconnecting the cores of a thousand core system.

Performance, algorithmic, and robustness attributes of perfect difference networks

Perfect difference networks (PDNs) that are based on the mathematical notion of perfect difference sets have been shown to comprise an asymptotically optimal method for connecting a number of nodes into a network with diameter 2. Justifications for, and mathematical underpinning of, PDNs appear in a companion paper. In this paper, we compare PDNs and some of their derivatives to interconnection networks with similar cost/performance, including certain generalized hypercubes and their hierarchical variants. Additionally, we discuss point-to-point and collective communication algorithms and derive a general emulation result that relates the performance of PDNs to that of complete networks as ideal benchmarks. We show that PDNs are quite robust, both with regard to node and link failures that can be tolerated and in terms of blandness (not having weak spots). In particular, we prove that the fault diameter of PDNs is no greater than 4. Finally, we study the complexity and scalability aspects of these networks, concluding that PDNs and their derivatives allow the construction of very low diameter networks close to any arbitrary desired size and that, in many respects, PDNs offer optimal performance and fault tolerance relative to their complexity or implementation cost.

Parallel computer vision on a reconfigurable multiprocessor network

A novel reconfigurable architecture based on a multiring multiprocessor network is described. The reconfigurability of the architecture is shown to result in a low network diameter and also a low degree of connectivity for each node in the network. The mathematical properties of the network topology and the hardware for the reconfiguration switch are described. Primitive parallel operations on the network topology are described and analyzed. The architecture is shown to contain 2D mesh topologies of varying sizes and also a single one factor of the Boolean hypercube in any given configuration. A large class of algorithms for the 2D mesh and the Boolean n-cube are shown to map efficiently on the proposed architecture without loss of performance. The architecture is shown to be well suited for a number of problems in low and intermediate level computer vision such as the FFT, edge detection, template matching, and the Hough transform. Timing results for typical low and intermediate level vision algorithms on a transputer based prototype are presented.