Low-density Parity-check Codeword Research Articles

Block Markov superposition transmission of LDPC codes

In this paper, based on the block Markov superposition transmission (BMST) technique, we present a new class of coupled low-density parity-check (LDPC) codes for the transport block (TB)-based transmission to improve the error-correcting performance. For encoding, the previous LDPC codewords corresponding to a TB (at prior time slot) are interleaved and superimposed onto the current LDPC codewords, resulting in the transmitted codewords. For decoding, the sliding window decoding algorithm with sum-product or min-sum implementations can be employed, inheriting a relatively low-latency decoding. A distinguished advantage of the proposed coded transmission over spatially coupled LDPC (SC-LDPC) codes is that the encoder/decoder of the proposed codes can be designed by reusing the encoder/decoder architecture of component block LDPC codes. To analyze the waterfall performance of BMST-LDPC code ensembles, we present the protograph-based EXIT chart analysis, which can efficiently predict the error-correcting performance in waterfall region. To analyze the error-floor performance of BMST-LDPC codes, we employ the genie-aided (GA) lower bound, which can efficiently predict the error-correcting performance in error-floor region. For ease of implementation, the BMST-LDPC codes are constructed by taking the (2, 4)-raptor-like LDPC codes or the 5G LDPC codes as the basic components. The numerical results reveal that the proposed codes can have capacity-approaching performance, exhibiting a gap of 0.007 ​dB away from the corresponding Shannon limit. They also reveal that, by using the proposed BMST construction, the error-correcting performance of the original 5G block LDPC codes can be significantly improved, achieving coding gains up to one dB over the AWGN channels and two dB over the fast fading channels.

Error Correction LDPC Encoder with Bit-Flipping Decoder

The communication method conveys information from the transmitter to the receiver over an intermediate medium. The competence of received information is determined by medium and clatter. There is a great need for robust error correction techniques with ever accumulative usage of wireless expedients such as portable electronic items and broadband modems. Wireless communication schemes depend on advanced error rectification techniques for their suitable functioning. Hence transferring and getting information with less or without error, while utilizing the accessible bandwidth is a foremost proposal, project necessities for present digital wireless communication systems comprising of high throughput, low power consumption, and less area. In this article, the functional analysis is performed for error control coding technique i.e., Low-Density-Parity-Check (LDPC) coding in terms of device utilization and power. The functional verification and the simulation are performed using Verilog HDL. Error correction techniques such as Linear block codes, RS codes, Convolutional codes are employed to implement forward error correction but as the constraint length increases the design of decoders becomes more complex. LDPC is a type of block code that is capable of correcting random errors. They are popular because of their eminent detection and correction capabilities. LDPC encoding technique provides high throughput and aims to improve BER when compared to conventional techniques. The decoding of LDPC codeword employs the Message Passing Algorithm, where each bit in a codeword is allocated to special nodes. The performance of these codes is hence better and easily attains Shannon’s limit than the previously used codes. Synthesis for the technique is performed and utilization reports are derived from the synthesis in Vivado.

Role of the Product λ′(0)ρ′(1) in Determining LDPC Code Performance

The objective of this work is to analyze the importance of the product λ ′ ( 0 ) ρ ′ ( 1 ) in determining low density parity check (LDPC) code performance, as far as its influence on the weight distribution function and on the decoding thresholds. This analysis is based on the 2006 paper by Di et al., as far as the weight distribution function is concerned, and on the 2018 paper by Vatta et al., regarding the LDPC decoding thresholds. In particular, the first paper Di et al. analyzed the relation between the above mentioned product and the minimum weight of an ensemble of random LDPC codewords, whereas in the second some analytical upper bounds to the LDPC decoding thresholds were determined. In the present work, besides analyzing the performance of an ensemble of LDPC codes through the outcomes of Di et al.’s 2006 paper, we give the relation between one of the upper bounds found in Vatta et al.’s 2018 paper and the above mentioned product λ ′ ( 0 ) ρ ′ ( 1 ) , thus showing its role in also determining an upper bound to LDPC decoding thresholds.

Efficient Decoding of LDM Core Layer at Fixed Receivers in ATSC 3.0

In order to decode an enhanced layer (EL) signal for a layered-division multiplexing (LDM) system at fixed receivers in ATSC 3.0, low-density parity-check (LDPC)/BCH decoding and successive interference cancellation should be performed to eliminate the core layer (CL) signal. For a high signal-to-noise ratio environment and sufficient low injection level of the EL signal, the CL bit-interleaved coded modulation decoder can easily achieve quasi error free for the whole LDPC codeword. However, for high injection levels, there may be still many erroneous bits in the parity part even after LDPC/BCH decoding since the ATSC 3.0 LDPC codes have the characteristic of unequal error protection due to the unequal weight distributions in their parity-check matrices. Therefore, ATSC 3.0 receivers should include re-encoding module for CL LDPC codes to completely recover the CL signal for LDM system. In this paper, we propose an efficient method to reconstruct CL signal in ATSC 3.0 LDM systems, which can be realized by a modified re-encoding after LDPC decoding of the CL signal. It significantly reduces the computational complexity and worst case latency without any loss of coding performance.

Design of LDPC Codes for Unequal ISI Channels

In this paper, we design an irregular low-density parity-check (LDPC) codes for unequal inter-symbol interference channels based on the modified extrinsic information transfer chart. During transmission, each LDPC codeword will be divided and transmitted to the different channels. The aim of this scheme is to avoid transmitting the whole codeword in a high error rate channel. The simulation results show that the proposed code optimized for both PR1 and PR2 channels can achieve a 0.2 coding gain over the codes designed specifically for each individual channel. When this simple code is applied to a perpendicular channel with these two targets, the coding gains of the proposed code is about 0.08 dB at the frame error rate of $10^{-3}$ .

The Analytical Description of Regular LDPC Codes Correcting Ability

Abstract The analytical description of regular LDPC (Low-Density Parity Check) codes correcting ability has been investigated. The statistical dependencies for the maximum number of corrected bits per the code word as a function of LDPC code word length and code rate are given based on multiple experimental analyses of LDPC check matrices. The analytical expressions are proposed for the cases of linear, exponential and polynomial approximations of given results. The most exact analytical formula is proved by criterion of the minimum divergence between the experimental and theoretical results.

Improving Burst Error Tolerance of LDPC-Centric Coding Systems in Read Channel

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We report on the use of low-density parity check (LDPC)-centric error correction coding (ECC) for magnetic recording read channel in the presence of significant burst errors. Since an LDPC code by itself is severely vulnerable to burst errors due to its soft-decision probability-based decoding, we focus on LDPC-centric concatenated coding in which LDPC code is used as inner code. To improve the burst error tolerance, we propose a hybrid LDPC-centric concatenated coding strategy in which one inner LDPC codeword is replaced by another codeword with much stronger burst error correction capability. This special inner codeword reveals the burst error location information, which can be leveraged by the inner LDPC code decoding to largely improve the overall robustness to burst errors. Using a hybrid BCH-LDPC/RS concatenated coding system as a test vehicle, we demonstrate a significant performance advantage over its RS-only and LDPC-only counterparts in the presence of three different types of burst errors. </para>

A scalable LDPC decoder ASIC architecture with bit-serial message exchange

We present a scalable bit-serial architecture for ASIC realizations of low-density parity check (LDPC) decoders. Supporting the architecture's potential, we describe a decoder implementation for a (256,128) regular-(3,6) LDPC code that has a decoded information throughput of 250 Mbps, a core area of 6.96 mm 2 in 180-nm 6-metal CMOS, and an energy efficiency of 7.56 nJ per uncoded bit at low signal-to-noise ratios. The decoder is fully block-parallel, with all bits of each 256-bit codeword being processed by 256 variable nodes and 128 parity check nodes that together form an 8-stage iteration pipeline. Extrinsic messages are exchanged bit-serially between the variable and parity check nodes to significantly reduce the interleaver wiring. Parity check node processing is also bit-serial. The silicon implementation performs 32 iterations of the min-sum decoding algorithm on two staggered codewords in the same pipeline. The results of a supplementary layout study show that the reduced wiring congestion makes the decoder readily scaleable up to the longer kilobit-size LDPC codewords that appear in important emerging communication standards.

Low-density Parity-check codes with run length limited (RLL) constraints

This paper addresses a new scheme by Vasic and Pedagani to combine low-density parity-check (LDPC) codes with run length limited (RLL) constraints. In this method, the RLL constraints are embedded into the LDPC codewords by deliberately flipping the bits of LDPC codewords that violate the RLL constraints. It is important to keep the number of flipped bits small in order to not overburden the LDPC decoder. In this paper, we introduce a method to control the number of flipped bits by using pseudorandom sequences. We present a new low-complexity iterative decoding and detection scheme to correct both the flipped bits and channel errors in a partial response channel. Analyses and simulation results show that the proposed method has good performance and reasonable complexity for (0,k) RLL constraints.