Low-cost SoC Research Articles

New LTE-A Low-Latency Detectors for Cognitive Radio on Low-Cost FPGA SoC

New LTE-A Low-Latency Detectors for Cognitive Radio on Low-Cost FPGA SoC

Low Memory Access Video Stabilization for Low-Cost Camera SoC.

Video stabilization is one of the most important features in consumer cameras. Even simple video stabilization algorithms may need to access the frames several times to generate a stabilized output image, which places a significant burden on the camera hardware. This high-memory-access requirement makes it difficult to implement video stabilization in real time on low-cost camera SoC. Reduction of the memory usage is a critical issue in camera hardware. This paper presents a structure and layout method to efficiently implement video stabilization for low-end hardware devices in terms of shared memory access amount. The proposed method places sub-components of video stabilization in a parasitic form in other processing blocks, and the sub-components reuse data read from other processing blocks without directly accessing data in the shared memory. Although the proposed method is not superior to the state-of-the-art methods applied in post-processing in terms of video quality, it provides sufficient performance to lower the cost of camera hardware for the development of real-time devices. According to my analysis, the proposed one reduces the memory access amount by 21.1 times compared to the straightforward method.

OpenCL Implementation of an Adaptive Disruption Predictor Based on a Probabilistic Venn Classifier

The ability and flexibility of the open computing language (OpenCL) for task parallelization in heterogeneous computing platforms [field-programmable gate array (FPGA), CPU, and GPU] are remarkable advantages when designing advanced data acquisition and processing systems. The use of FPGA devices in data acquisition devices increases the capabilities of traditional data acquisition systems, thus allowing the implementation of complex mathematical algorithms with the acquired data. This paper shows an OpenCL implementation of an adaptive probabilistic disruption predictor for fusion devices implemented in a Cyclone V SoC device with an ARM processor, the FPGA logic, and an analog to digital converter. This paper describes the methodology used, the hardware/software system architecture, and the implementation results. The work highlights the critical aspects involved in designing these OpenCL-based systems and, in particular, the implementation of the board support package. This paper also presents the aspects such as the significant differences in the design flow concept between FPGA and GPU OpenCL implementations and how to optimize the FPGA implementation with OpenCL. The results show that it is possible to make predictions with computation times shorter than $500~\mu \text{s}$ when using this low-cost SoC.

Small-area low-power heart condition monitoring system using dual-mode SAR-ADC for low-cost wearable healthcare systems.

Heart rate monitoring is useful to detect many cardiovascular diseases. It can be implemented in a small device with low power consumption, and it can exploit low-cost piezoelectric pressure sensors to measure heart rate. However, it is also desirable to transmit heartbeat waveform for emergency treatment, which significantly increases transmission power. In this paper, a low-cost wireless heart condition monitoring SoC is proposed. It can monitor and transmit both heart rate and heartbeat waveform, but the hardware is extremely simplified to achieve in a small package. By slight modification of successive-approximation analog-digital converter, it can count heart rate and read out heartbeat waveform with the same hardware. In the normal mode, only an 8-bit heart rate is transmitted for power reduction. If the heart rate is out of a given range, it goes to the emergency mode and a 10-bit heartbeat waveform is transmitted for fast treatment. The fabricated chip size is 1.1 mm2 in 0.11 μ m CMOS technology, including the radio-frequency transmitter. The measured power consumption is 161.8 μ W in normal mode and 507.3 μ W in emergency mode, respectively. The proposed SoC achieves low-cost, small area, and low-power. It is useful as part of a disposable healthcare system.

New Movable Plate for Efficient Millimeter Wave Vertical on-Chip Antenna

A new movable plate concept is presented in this paper to realize mm-wave vertical on-chip antennas through MEMS based post-processing steps in a CMOS compatible process. By virtue of its vertical position, the antenna is isolated from the lossy Si substrate and hence performs with a better efficiency as compared to the horizontal position. In addition, the movable plate concept enables polarization diversity by providing both horizontal and vertical polarizations on the same chip. Through a first iteration fractal bowtie antenna design, dual band (60 and 77 GHz) operation is demonstrated in both horizontal and vertical positions without any change in dimensions or use of switches for two different mediums (Si and air). To support the movable plate concept, the transmission line and antenna are designed on a flexible polyamide, where the former has been optimized to operate in the bent position. The design is highly suitable for compact, low cost and efficient SoC solutions.

An Embedded Systems Laboratory to Support Rapid Prototyping of Robotics and the Internet of Things

This paper describes a new approach for a course and laboratory designed to allow students to develop low-cost prototypes of robotic and other embedded devices that feature Internet connectivity, I/O, networking, a real-time operating system (RTOS), and object-oriented C/C++. The application programming interface (API) libraries provided permit students to work at a higher level of abstraction. A low-cost 32-bit SOC RISC microcontroller module with flash memory, numerous I/O interfaces, and on-chip networking hardware is used to build prototypes. A cloud-based C/C++ compiler is used for software development. All student files are stored on a server, and any Web browser can be used for software development. Breadboards are used in laboratory projects to rapidly build prototypes of robots and embedded devices using the microcontroller, networking, and other I/O subsystems on small breakout boards. The commercial breakout boards used provide a large assortment of modern sensors, drivers, display ICs, and external I/O connectors. Resources provided include eBooks, laboratory assignments, and extensive Wiki pages with schematics and sample microcontroller application code for each breakout board.

Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player

We propose a low cost and stand-alone platform-based SoC for H.264/AVC decoder, whose target is practical mobile applications such as a handheld video player. Both low cost and stand-alone solutions are particularly emphasized. The SoC, consisting of RISC core and decoder core, has advantages in terms of flexibility, testability and various I/O interfaces. For decoder core design, the proposed H.264/AVC coprocessor in the SoC employs a new block pipelining scheme instead of a conventional macroblock or a hybrid one, which greatly contribute to reducing drastically the size of the core and its pipelining buffer. In addition, the decoder schedule is optimized to block level which is easy to be programmed. Actually, the core size is reduced to 138 KGate with 3.5 kbyte memory. In our practical development, a single external SDRAM is sufficient for both reference frame buffer and display buffer. Various peripheral interfaces such as a compact flash, a digital broadcast receiver and a LCD driver are also provided on a chip.