Low-cost Field Programmable Gate Array Devices Research Articles

FPGA-based neural network accelerators for millimeter-wave radio-over-fiber systems.

With rapidly developing high-speed wireless communications, the 60 GHz millimeter-wave (mm-wave) frequency range has attracted extensive interests, and radio-over-fiber (RoF) systems have been widely investigated as a promising solution to deliver mm-wave signals. Neural networks have been proposed and studied to improve the mm-wave RoF system performances at the receiver side by suppressing both linear and nonlinear impairments. However, previous studies of neural networks in mm-wave RoF systems all focus on the use of off-line processing with high-end GPUs or CPUs, which are not practical for low power-consumption, low-cost and limited computation platform applications. To solve this issue, in this paper we investigate neural network hardware accelerator implementations for mm-wave RoF systems for the first time using the field programmable gate array (FPGA), taking advantage of the low power consumption, parallel computation, and reconfigurablity features of FPGA. Both the convolutional neural network (CNN) and binary convolutional neural network (BCNN) hardware accelerators are demonstrated. In addition, to satisfy the low-latency requirement in mm-wave RoF systems and to enable the use of low-cost compact FPGA devices, a novel inner parallel computation optimization method for implementing CNN and BCNN on FPGA is proposed. It is shown that compared with the popular embedded processor (ARM Cortex A9) execution latency, the proposed FPGA-based hardware accelerator reduces the processing delay in mm-wave RoF systems by about 99.45% and 92.79% for CNN and BCNN, respectively. Compared with non-optimized FPGA implementations, results show that the proposed inner parallel computation method reduces the processing latency by about 44.93% and 45.85% for CNN and BCNN, respectively. In addition, compared with the GPU implementation, the latency of CNN implementation with the proposed optimization method is reduced by 85.49%, while the power consumption is reduced by 86.91%. Although the latency of BCNN implementation with the proposed optimization method is larger compared with the GPU implementation, the power consumption is reduced by 86.14%. The demonstrated FPGA-based neural network hardware accelerators provide a promising solution for mm-wave RoF systems.

FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices

The design of cryptographic engines for the Internet of Things (IoT) edge devices and other ultralightweight devices is a crucial challenge. The emergence of such resource-constrained devices raises significant challenges to current cryptographic algorithms. PHOTON is an ultra-lightweight cryptographic hash function targeting low-resource devices. The currently implemented hardware architectures of PHOTON hash function utilize a large amount of resources and have low operating frequencies with a low rate of throughputs. Maximum operating frequency and throughput of PHOTON architecture can be improved but at the cost of larger area utilization. Therefore, to improve the area-performance trade-offs of PHOTON hash function, an iterative architecture is implemented in this work. The concern is with the most lightweight version of PHOTON hash function with the hash size of 80 bits. It is implemented and verified on several Xilinx and Altera Field Programmable Gate Array (FPGA) devices using their synthesis and simulation tools. Low-cost and high-processing FPGA devices were both considered. The design is optimized for performance, whereas the area utilization is also taken into consideration. The overall performance and logic utilization are benchmarked with the existing implementations. The results show an improvement rate of 10.26% to 51.04% in the speed performance and a reduction rate of 7.55% to 60.64% in area utilization compared to existing implementations of PHOTON hash functions.

A 2.3-ps RMS Resolution Time-to-Digital Converter Implemented in a Low-Cost Cyclone V FPGA.

We present a nonuniform multiphase (NUMP) method to construct a high-resolution time-to-digital converter (TDC) for low-cost field-programmable gate array (FPGA) devices. The NUMP method involves a system clock being passed through a series of delay elements to generate multiple clocks with different phase shifts. The phases of the rising and falling edges of all the clocks are sorted in order and the states of all the clocks are latched when a hit signal arrives. The sizes of the time bins (and precision) of the NUMP method are not limited by the uniformity and minimum value of the time delays of the delay lines. In theory, any delay sources with small jitters in an FPGA, not just very fine carry chains, can be used in the NUMP method to delay and randomize the clocks. Thus, the NUMP method can achieve excellent TDC timing resolutions in low-cost FPGAs without very fine delay lines. We implemented four NUMP TDC channels in a low-cost FPGA device (an Altera Cyclone V 5CEBA4F23C7N). The performance of the four NUMP TDCs was evaluated using both internal and external pulses. The root mean square (rms) for the timing resolution measured using the internal and the external pulses with short-time intervals (less than 1 ns) was 2.3 and 5.2 ps, respectively. A 14.1-ps rms timing resolution was measured at a time interval of 517 ns. The NUMP method is suitable for applications that require a number of high-performance TDC channels in a low-cost FPGA.

Efficient FPGA-based architecture of an automatic wheeze detector using a combination of MFCC and SVM algorithms

This paper proposes a new hardware implementation of an automatic wheeze detector in pulmonary sounds. The proposed system is based on the combination of Mel-frequency cepstral coefficients (MFCC) feature extraction method and a support vector machine (SVM) classifier. It has been implemented on a field programmable gate array (FPGA) chip using the Xilinx System Generator (XSG) programming tool and the Nexys-4 development board, which is built around the low-cost Artix-7 FPGA device. The LIBSVM library has been used to extract the SVM parameters during the training phase in the Matlab environment, then the MFCC feature extraction and the SVM testing phase are performed on the FPGA chip. Two hardware architectures (default and optimized) of the SVM classifier are implemented and compared in terms of resource utilization, maximum operating frequency, and power consumption for the Artix-7 XC7A100T FPGA Chip. The detection rates obtained by the fixed-point XSG implementation are presented and compared to those obtained by the floating-point Matlab simulation. It has been also compared to existing methods in terms of the detection rates and the characteristics of its implementation.

Pipelined Architecture of Multi-Band Spectral Subtraction Algorithm for Speech Enhancement

In this paper, a new pipelined architecture of the multi-band spectral subtraction algorithm has been proposed for real-time speech enhancement. The proposed hardware has been implemented on field programmable gate array (FPGA) device using Xilinx system generator (XSG), high-level programming tool, and Nexys-4 development board. The multi-band algorithm has been developed to reduce the additive colored noise that does not uniformly affect the entire frequency band of useful signal. All the algorithm steps have been successfully implemented on hardware. Pipelining has been employed on this hardware architecture to increase the data throughput. Speech enhancement performances obtained by the hardware architecture are compared to those obtained by MATLAB simulation using simulated and actual noises. The resource utilization, the maximum operating frequency, and power consumption are reported for a low-cost Artix-7 FPGA device.

A single chip FPGA-based solution for controlling of multi-unit PMSM motor with time-division multiplexing scheme

The use of multiple unit controllers for parallel processing of multi-unit motor drive systems can significantly reduce the execution time of the control algorithm. However, this approach does not only increase the system cost but also incurs in additional cost of hardware and software interconnections. This paper presents a fully integrated single chip field programmable gate array (FPGA) based solution for controlling of an independent multi-unit permanent magnet synchronous motor (PMSM) drive system with space vector pulse width modulation (SVPWM) based vector control. For multi-unit motor systems, the complexity of control algorithms often exceeds the resource availability of low-cost FPGA devices. Thus, a system-level time-division multiplexing scheme applicable for multi-motor control systems is proposed. Using the proposed method, large identical complex control algorithms can be simplified into a single compact algorithm, which is fitted and configured into a low-cost FPGA. Simulation modeling and experimental results are shown, confirming the effectiveness of a multi-unit PMSM motor drive system using an inexpensive controller based on system-level time-division multiplexing scheme, which can operate simultaneously with robustness under different operating conditions.

Low‐cost and high‐speed hardware implementation of contrast‐preserving image dynamic range compression for full‐HD video enhancement

This study presents a cost-efficient and high-performance field programmable gate array (FPGA)-based hardware implementation of a contrast-preserving image dynamic range compression algorithm, which is an important function used in modern digital video cameras and displays to improve visual quality of standard dynamic range colour images (8 bits/channel). To achieve this purpose, a hardware-friendly approximation to an existing fast dynamic range compression with local contrast preservation (FDRCLCP) algorithm is proposed. The computation of the proposed approximated FDRCLCP algorithm requires only fixed-point unsigned binary addition, multiplication, and bit-shifting. Moreover, the proposed hardware implementation uses a line buffer instead of a frame buffer to process whole image data. These advantages significantly improve throughput performance and reduce memory requirement of the system. The FPGA implementation of the proposed algorithm requires only about 98 K bits on-chip memory and achieves about 170.24 MHz operating frequency by using an Altera Cyclone II device. This is a large improvement compared with the existing results as it is quick enough to process full high-definition videos (1920 × 1080 pixels) at least 80 frames per second using a low-cost FPGA device.

Design and implementation of a novel sliding mode sensing architecture for capacitive MEMS accelerometers

We propose novel feedback control and sensing schemes based on sliding mode control (SMC) for closed-loop micro-accelerometers as alternative digital control architectures to sigma–delta (ΣΔ) approaches. The under-damped micro-device has been designed in Coventorware, fabricated in SOIMUMPs (25 µm thick structural layer) technology and experimentally characterized using a Polytec MSA-500 (micro-system analyzer) equipment. To verify the system architecture robustness, the application of SMC is extended to an over-damped accelerometer model. In either case, the SMC demonstrates the repositioning of the proof mass to null position; however, the over-damped model exhibits shorter transition time (15 ms for 1g acceleration) due to the increased damping. In addition to that, we extend the usage of SMC beyond the classical actuation problem to a novel sensing problem where we demonstrate the extraction of the external acceleration measurement from the switching behavior along the sliding surface. An optimized fixed-point implementation is targeted on a field-programmable gate array (FPGA) using rapid prototyping methodology, where the new proposed method has been compared for reference with a control scheme that employs a ΣΔ modulator. The SMC-based architecture is advantageous in terms of hardware complexity, and the control of the number of degrees of freedom required by an inertial measurement unit can be accommodated on a low-cost FPGA device. SMC offers a sound theoretical framework for the nonlinear control of inertial sensors.