Low-complexity Low-density Parity-check Research Articles

A Low-Complexity Neural Normalized Min-Sum LDPC Decoding Algorithm Using Tensor-Train Decomposition

Compared with traditional low-density parity-check (LDPC) decoding algorithms, the current model-driven deep learning (DL)-based LDPC decoding algorithms face the disadvantage of high computational complexity. Based on the Neural Normalized Min-Sum (NNMS) algorithm, we propose a low-complexity model-driven DL-based LDPC decoding algorithm using Tensor-Train (TT) decomposition and syndrome loss function, called TT-NNMS+ algorithm. Our experiments show that the proposed TT-NNMS+ algorithm is more competitive than the NNMS algorithm in terms of bit error rate (BER) performance, memory requirement and computational complexity.

Low-Complexity LDPC Decoding Algorithm Based on Layered Vicinal Variable Node Scheduling

The informed dynamic scheduling (IDS) strategies for the low-density parity check (LDPC) decoding have shown superior performance in error correction and convergence speed, particularly those based on reliability measures and residual belief propagation (RBP). However, the search for the most unreliable variable nodes and the residual precomputation required for each iteration of the IDS-LDPC increases the complexity of the decoding process which becomes more sequential, making it hard to exploit the parallelism of signal processing algorithms available in multicore platforms. To overcome this problem, a new, low-complexity scheduling system, called layered vicinal variable nodes scheduling (LWNS) is presented in this paper. With this LWNS, each variable node is updated by exchanging intrinsic information with all its associated control and variable nodes before moving to the next variable node updating. The proposed scheduling strategy is fixed by a preprocessing step of the parity control matrix instead of calculation of the residuals values and by computation of the most influential variable node instead the most unreliable metric. It also allows the parallel processing of independent Tanner graph subbranches identified and grouped in layers. Our simulation results show that the LWNS BP have an attractive convergence rate and better error correction performance with low complexity when compared to previous IDS decoders under the white Gaussian noise channel (AWGN).

Low-Complexity High-Throughput Bit-Wise LDPC Decoder

Emerging standards for wireless communications in the 60-GHz band, such as WiGig and IEEE 802.11ad, require high throughput between 1.5 and 6 Gb/s. These standards use adaptive low-density parity-check (LDPC) codes for high error correction capability. Most research studies on LDPC decoders have focused on low area implementations, to improve throughput. We previously developed a bit-serial first two minimum-value generator without bit error rate (BER) performance degradation. This paper presents a low-complexity bit-wise LDPC decoder based on bit-serial first two minimum-value generator for a high-data-rate LDPC decoder. We use the throughput-to-area ratio (TAR) metric to compare with other 802.11ad LDPC decoders.

Adaptive deactivation and zero-forcing scheme for low-complexity LDPC decoders

A modified message propagation algorithm is proposed for a low-complexity decoder of low-density parity-check (LDPC) codes, which controls the information propagated from variable and check nodes.The proposed threshold-based node deactivation for variable nodes and zero-forcing scheme for check nodes remarkably reduce decoding complexity required for similar error performance. In the proposed scheme, different thresholds, which are determined from the base matrix of the LDPC codes, are applied for each type of variable node. In addition, thresholds for deactivating variable nodes are increased while the decoding process is operated for a reduction in decoding complexity without early error floor, which is a drawback of the conventional threshold-based deactivation scheme. Simulation results show that the proposed scheme enables normalized min-sum decoders to decode successfully with less complexity than the conventional threshold-based deactivating scheme.

An Efficient Joint Channel-Network Decoder for Multiuser Diversity Network Codes With LDPC Coding

Diversity network codes (DNCs) were recently proposed for multiuser cooperative networks, where nonbinary network codes are superimposed over channel codes to yield high diversity gains. In this letter, we present a joint iterative channel-network decoder for use at the base station in a system employing a DNC. The scheme is based on hybrid soft/hard message passing between constituent low-complexity low-density parity-check (LDPC) decoders. It is shown that the formation of the extrinsic log-likelihood ratios to be passed between the LDPC decoders has a low-complexity implementation involving a set of permutation operations together with the well-known Jacobian logarithm. The proposed joint channel-network decoder has a significantly reduced complexity compared with the decoding structure originally presented for maximum-diversity-achieving DNCs, and achieves significant coding gain as well as full diversity gain.

Approximated Box-Plus Decoding of LDPC Codes

The problem of how to approximate effectively the box-plus operation used in sum-product algorithm (SPA) decoding of low-density parity-check (LDPC) codes has been widely investigated over the past years of research. This letter deals, for the first time, with a totally different approach where a very simple, yet efficient, decoding algorithm for LDPC codes is proposed. The tremendous savings, in terms of required number of operations, offered by the proposed algorithm and its near optimal SPA performance are making it appealing in practical applications requiring very low complexity LDPC decoding architectures.

Low complexity LDPC decoder with modified Sum-Product algorithm

This paper describes an efficient implementation of the Sum-Product Algorithm (SPA) within a Low Density Parity Check (LDPC) code decoder, where a horizontal process correction term is used to improve the decoding performance of the Min-Sum algorithms. The correction term is implemented as a look-up table. The algorithm uses the correction term redundancy by means of a coordinate transformation to reduce the hardware complexity. Simulations and hardware tests indicate that the decoding performance is very good with the appropriate look-up table.

Selective max‐min algorithm for low‐density parity‐check decoding

With the growing importance of error correction in different communication systems, using an efficient and easily implementable code is always appreciated. One of the most important codes is the low-density parity-check (LDPC) code. Two main iterative decoding algorithms are usually used, namely the sum-product (SP) algorithm (also referred to as belief propagation) and the min-sum (MS). The SP algorithm is more accurate but suffers from very high complexity. On the other hand, the MS algorithm has a much lower complexity at the expense of some performance degradation. To handle this performance degradation, many algorithms were presented in the literature as improvements for the MS, like the scaled MS and the offset MS. However, all those improved algorithms are more complex than the traditional MS. In this study, an efficient and low complexity LDPC decoding algorithm, called selective max-min (SMM), is proposed. The SMM performance is closer to SP than to MS as long as the average number of ones per column in the parity check matrix is around or less than 4 (which is the case for most of the communication systems using LDPC). On the other hand, the SMM exhibits only a minor complexity increase over traditional MS making it suitable for practical implementation.

Low-Complexity Memory Access Architectures for Quasi-Cyclic LDPC Decoders

Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.

Cavity Quantum Electrodynamics (CQED)-Based Quantum LDPC Encoders and Decoders

Quantum information processing (QIP) relies on delicate superposition states that are sensitive to interactions with environment, resulting in errors. Moreover, the quantum gates are imperfect so that the use of quantum error correction coding (QECC) is essential to enable the fault-tolerant computing. The QECC is also important in quantum communication and teleportation applications. The most critical gate, i.e., the CNOT gate, has been implemented recently as a probabilistic device by using integrated optics. CNOT gates from linear optics provide only probabilistic outcomes and, as such, are not suitable for any meaningful quantum computation (on the order of thousand qubits and above). In this paper, we show that arbitrary set of universal quantum gates and gates from Clifford group, which are needed in QECC, can be implemented based on cavity quantum electrodynamics (CQED). Moreover, in CQED technology, the use of the controlled-Z gate instead of the CNOT gate is more appropriate. We then show that encoders/decoders for quantum low-density parity-check (LDPC) codes can be implemented based on Hadamard and controlled-Z gates only using CQED. We also discuss quantum dual-containing and entanglement-assisted codes and show that they can be related to combinatorial objects known as balanced incomplete block designs (BIBDs). In particular, a special class of BIBDs-Steiner triple systems (STSs)-yields to low-complexity quantum LDPC codes. Finally, we perform simulations and evaluate the performance of several classes of large-girth quantum LDPC codes suitable for implementation in CQED technology against that of lower girth entanglement-assisted codes and dual-containing quantum codes.

Binary SOVA and Nonbinary LDPC Codes for Turbo Equalization in Magnetic Recording Channels

Nonbinary low-density parity check (LDPC) codes can provide coding gains over binary LDPC codes at the cost of increased complexity. For magnetic recording channels, optimal detectors for the nonbinary codes are symbol-based, which are significantly more complex than binary detectors. In this paper, we investigate the feasibility of using much less complex bit-based soft output Viterbi algorithm (SOVA) as a channel detector for nonbinary LDPC codes and performing turbo iterations between the SOVA and the nonbinary LDPC decoder. We show that performance gains can still be obtained by the turbo iterations by using the bit-based SOVA, although the performance gains are suboptimal to the symbol-based detectors. This scheme can be useful in low-complexity nonbinary LDPC coding systems.

Low-complexity girth-8 high-rate moderate length QC LDPC codes

A low-complexity method for constructing a large class of high-rate girth-8 quasi-cyclic low-density parity-check (LDPC) codes with moderate length 1000 < n < 10 000 is presented. This method is based on combining configurations with incidence matrices composed of cyclic permutation matrices and Tanner graph girth at least 8. Shortened lattice codes of length n < 380 and girth 8 are employed as component codes. From the performance perspective, the resulting codes are comparable to their counterparts such as random-like and shortened array LDPC codes.

Low-complexity LDPC coded BICM-ID with orthogonal modulations

A low-complexity low density parity check (LDPC) coded bit-interleaved coded modulation with iterative decoding (BICM-ID) scheme with orthogonal modulations is proposed. With a novel mapping strategy of coded bits to symbols, the proposed scheme is equivalent to a generalised LDPC code with Hadamard constraints and thus orthogonal demodulation can be merged into the iterative LDPC decoding process, resulting in a simpler implementation and a lower computational complexity.