Low-complexity Bit-parallel Multipliers Research Articles

Low complexity bit-parallel multiplier for [formula omitted] defined by repeated polynomials

Wu recently proposed three types of irreducible polynomials for low-complexity bit-parallel multipliers over F2n. In this paper, we consider new classes of irreducible polynomials for low-complexity bit-parallel multipliers over F2n, namely, repeated polynomial (RP). The complexity of the proposed multipliers is lower than those based on irreducible pentanomials. A repeated polynomial can be classified by the complexity of bit-parallel multiplier based on RPs, namely, C1, C2 and C3. If we consider finite fields that have neither a ESP nor a trinomial as an irreducible polynomial when n≤1000, then, in Wu’s result, only 11 finite fields exist for three types of irreducible polynomials when n≤1000. However, in our result, there are 181, 232(52.4%), and 443(100%) finite fields of class C1, C2 and C3, respectively.

Bit-Parallel Polynomial Basis Multiplier for New Classes of Finite Fields

In this paper, three small classes of finite fields GF$(2^m)$ are found for which low complexity bit-parallel multipliers are proposed. The proposed multipliers have lower complexities compared to those based on the irreducible pentanomials. It is also shown that there does not always exist an irreducible all-one polynomial, equally-spaced polynomial, or trinomial for the new classes of fields.

Low-Complexity Bit-Parallel Multipliers for a Class of Gf(2m) Based on Modified Booth’s Algorithm

This investigation presents an effective algorithm for computing multiplication over a class of GF(2m) based on both irreducible all one polynomials (AOPs) and equally spaced polynomials (ESPs). The proposed AOP-based multiplier uses the modified Booth’s algorithm to develop a new multiplexer-based bit-parallel multiplier that is simple and modular and such properties are important for VLSI hardware implementation. The multiplier requires [m/4](m+1) MUX4×1 and (1.5m2 +0.5m-1) XOR gates. Its time delay is not greater than TM +(3+log2[m/4])TX, where TM and TX are the time delays of MUX4X1 and 2-input XOR gate, respectively. For a certain degree, an irreducible ESP with a high degree can be obtained from a corresponding irreducible AOP with a relatively very low degree. Using the subword parallel processing, the proposed AOP-based multiplier with low degree can also be adopted to realize ESP-based multipliers with high degrees.

Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials

In this paper, we consider the design of bit-parallel canonical basis multipliers over the finite field GF(2m) generated by a special type of irreducible pentanomial that is used as an irreducible polynomial in the Advanced Encryption Standard (AES). Explicit formulas for the coordinates of the multiplier are given. The main advantage of our design is that some of the expressions obtained are common to any irreducible polynomial, so our multiplier can be generalized to perform the multiplication over general irreducible polynomials. Moreover, the obtained expressions can be easily converted to parameterizable code using hardware description languages. The theoretical complexity analysis also shows that our bit-parallel multipliers present a reduced number of xor gates with respect to the best known results found in the literature

Low-Complexity Bit-Parallel Multiplier over GF(2m) Using Dual Basis Representation

Recently, cryptographic applications based on finite fields have attracted much attention. The most demanding finite field arithmetic operation is multiplication. This investigation proposes a new multiplication algorithm over GF(2m) using the dual basis representation. Based on the proposed algorithm, a parallel-in parallel-out systolic multiplier is presented. The architecture is optimized in order to minimize the silicon covered area (transistor count). The experimental results reveal that the proposed bit-parallel multiplier saves about 65% space complexity and 33% time complexity as compared to the traditional multipliers for a general polynomial and dual basis of GF(2m).

Low Complexity Bit-Parallel Multiplier for GF(2^m) Defined by All-One Polynomials Using Redundant Representation

This paper presents a new bit-parallel multiplier for the finite field GF(2/sup m/) defined by an irreducible all-one polynomial. In order to reduce the complexity of the multiplier, we introduce a redundant representation and use the well-known multiplication method proposed by Karatsuba. The main idea is to combine the redundant representation and the Karatsuba method to design an efficient bit-parallel multiplier. As a result, the proposed multiplier requires about 25 percent fewer AND/XOR gates than the previously proposed multipliers using an all-one polynomial, while it has almost the same time delay as the previously proposed ones.

Low complexity bit-parallel multipliers for GF(2m) with generator polynomial xm + xk + 1

A low complexity bit-parallel standard basis multiplier for GF(2m) with polynomial generator xm + xk + 1 is presented. The proposed multiplier uses a significantly smaller number of XOR/AND gates than the fastest known multipliers, while having a comparable logarithmic computing time.

Low complexity bit-parallel multipliers for a class of finite fields

New implementations of bit-parallel multipliers for a class of finite fields are proposed. The class of finite fields is constructed with irreducible AOPs (all one polynomials) and ESPs (equally spaced polynomials). The size and time complexities of our proposed multipliers are lower than or equal to those of the previously proposed multipliers of the same class.