Low Common Mode Noise Research Articles

Power Module With Low Common-Mode Noise and High Reliability

Power Module With Low Common-Mode Noise and High Reliability

Improved Packaging of Power Module with Low-Permittivity Material for Low Common-Mode Noise and High Reliability

Improved Packaging of Power Module with Low-Permittivity Material for Low Common-Mode Noise and High Reliability

A Novel Interleaved Parallel Cascaded Three-Level PFC With Low Inductance Volt-Second and Low Common-Mode Noise

Interleaved parallel cascaded multilevel technology is an attractive approach for converters to achieve high efficiency, high-power density, and high modularity. In this letter, a novel single-phase interleaved parallel cascaded three-level (IPC-TL) power factor correction (PFC) converter is proposed. It is formed by cascading two interleaved parallel totem-pole PFC cells. The proposed topology exhibits the merits of lower inductance volt-second and inductor current ripples, lower common-mode noise, and lower control cost, compared with the traditional IPC-TL topology. A laboratory-scale experimental prototype is developed to verify the effectiveness of the proposed topology.

Non-Isolated DC-DC Converters With Low Common-Mode Noise by Using Split-Winding Configuration

The common-mode (CM) noise in nonisolated dc-dc converters is mainly caused by the displacement current through the high <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> node in the circuit and the associated parasitic capacitance, and it may cause electromagnetic interference (EMI) to the surrounding equipments. To reduce the original CM noise and shrink the EMI filter size of non-isolated dc-dc converters, CM noise cancellation methods have been proposed, including the symmetry circuit, balancing technique, passive cancellation and CM voltage cancellation. In these methods, additional components or windings are required for reducing the CM noise. In this article, a new CM noise cancellation method in non-isolated dc–dc converters is proposed by adopting a split-winding configuration. Compared to the existing CM noise cancellation methods which require additional components, the proposed method in the buck, boost and single-ended primary-inductor converter (SEPIC) converters which runs in voltage step-up mode has the identical volume as their conventional circuit configurations. The proposed method is verified for a buck converter by experiment.

Extended Range Bridgeless PFC Converter With High-Voltage DC Bus and Small Inductor

Utility power lines voltage levels vary in different geographical locations, ranging from 208 to 480 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> . Power factor correction (PFC) converters are typically designed for a particular input voltage and do not accept a wide range of line voltages. This results in multiple product designs and revisions and increased production costs to accommodate the various ac voltage levels used around the world. A PFC converter capable of coping with a wide input voltage range, from 90 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> up to 530 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> , would significantly decrease costs and streamline development. In this article, an extended input voltage range PFC converter is proposed, which provides a high and almost flat efficiency curve throughout the entire operating voltage range with an 800 VDC bus voltage. The proposed converter has a flexible bridgeless structure with simple control, low-current ripples, low common mode noise, and startup inrush current handling capabilities. Theoretical analysis and waveforms are discussed and experimental results for a 2-kW prototype are given, thereby validating the expected behavior. The operation of the proposed extended input voltage range PFC converter is also compared to the traditional totem-pole PFC showing more than 1% efficiency improvements at full load and a higher power factor in the proposed design.

Flexible Mode Bridgeless Boost PFC Rectifier With High Efficiency Over a Wide Range of Input Voltage

For the conventional PFC rectifiers, the high efficiency cannot be achieved over a wide input range, and the efficiency will be greatly decreased at low-input voltages. In order to overcome the efficiency bottleneck under low-line input, a flexible mode bridgeless boost power factor correction (PFC) rectifier is proposed in this paper. According to the input voltage, the proposed rectifier can be flexibly adapted to the suitable operating mode to obtain the maximum efficiency. Meanwhile, the circuit components can be reused by different operating modes, so the extra cost is low. In the proposed rectifier, a back-to-back bridgeless boost PFC topology is adopted at high-line conditions and a three-level bridgeless boost PFC topology is rebuilt to reduce the switching losses at low-line conditions. Compared with the traditional bridgeless boost PFC rectifier, an extra low-voltage bidirectional switch (usually composed of two switches) is added, so the increased cost is low. In addition, the low common-mode noise can be achieved at both high- and low-line conditions due to the direct connection between the input mains and the output electrolytic capacitor. The detailed principle analysis about the proposed rectifier is presented in this paper. Finally, an experimental prototype is built to verify the feasibility and the effectiveness of the proposed topology.

A novel single-phase AC–DC bridgeless boost converter for PFC application

ABSTRACTA novel single-phase AC–DC bridgeless boost power factor correction (PFC) converter is proposed in this paper. This converter is constructed by paralleling a boost and a buck–boost topology. It features a solid connection between the input and output ground terminals leading to low common mode noise. Moreover, it possesses a high PFC performance which can satisfy IEC-61000-3-2 Class D Limits completely and only two semiconductors conducting in the current-flowing path. In addition, the two power switches are driven by the same control signal resulting in a simple controller. The detailed circuit operation principle in discontinuous conduction mode is presented. A simulated model established by PSIM software and a lab prototype is designed to validate the effectiveness of this proposed PFC converter.

A 41dB Gain Control Range 6th-Order Band-Pass Receiver Front-End Using CMOS Switched FTI

A 41dB gain control range 6 th -order band-pass receiver front-end (RFE) using CMOS switched frequency translated impedance (FTI) is presented in a 40 nm CMOS technology. The RFE consists of a frequency tunable RF band-pass filter (BPF), IQ gm cells, and IQ TIAs. The RF BPF has wide gain control range preserving constant filter Q and pass band flatness due to proposed pre-distortion scheme. Also, the RF filter using CMOS switches in FTI blocks shows low clock leakage to signal nodes, and results in low common mode noise and stable operation. The baseband IQ signals are generated by combining baseband Gm cells which receives 8-phase signal outputs down-converted at last stage of FTIs in the RF BPF. The measured results of the RFE show 36.4 dB gain and 6.3 dB NF at maximum gain mode. The pass-band IIP3 and out-band IIP3@20 MHz offset are -10 dBm and +12.6 dBm at maximum gain mode, and +14 dBm and +20.5 dBm at minimum gain mode, respectively. With a 1.2 V power supply, the current consumption of the overall RFE is 40 mA at 500 MHz carrier frequency.

A Comparative Study of Z-Source Inverter Fed Three-Phase IM Drive with CSI and VSI fed IM

This paper cite comparative performance characteristics of Z-Source inverter fed IM drives with mostly used VSI & CSI fed IM drives. ZSI has both voltages buck and boost capabilities as they allow inverters to be operated in the shoot through state. It employs an exclusive Z-Source network (LC component) to dc-link the main inverter circuit to the power source (rectifier). By controlling the shoot-through duty cycle, the inverter system using IGBTS reduces the line harmonics, improves power factor, increases reliability and extends output voltage range. It has reduced harmonics, low switching stress power and low common mode noise as compared to VSI. Simulation results are given to compare the behavior of conventional and proposed topology and also demonstrate the new features of the improved topology i.e ZSI fed IM. Simulation results of ZSI fed IM gives different performance characteristics as compared to VSI & CSI fed IM drives such as its stator & rotor current characteristics, speed characteristics , torque characteristics which put a gloss on the VSI fed IM performance. DOI: http://dx.doi.org/10.11591/ijpeds.v3i3.3869

Analysis of Common-Mode Noise for Weakly Coupled Differential Serpentine Delay Microstrip Line in High-Speed Digital Circuits

This study investigates the mechanisms of generation of the transient transmission common-mode noise in a differential serpentine delay line under weak coupling condition. The generation mechanism and the frequency of common-mode noise are investigated with reference to the time-domain transmission waveform and the differential-to-common mode conversion mixed-mode S-parameters using the circuit solver HSPICE and 3-D full-wave simulator HFSS, respectively. The generation mechanisms of common-mode noise include length mismatch between vertical-turn-coupled traces, the length effect of parallel-coupled traces, and the crosstalk noise effect. Moreover, a graphical method based on wave tracing is presented to illustrate the cancellation mechanism of near-end common-mode noise for the symmetrical differential serpentine delay line. Some practical, commonly used layout routings of the differential serpentine delay line are investigated. Some important design guidelines are provided to help design differential serpentine delay line with low common-mode noise. A comparison between simulated and measured results validates the equivalent circuit model and analytical approach.

Reducing Common-Mode Noise in Two-Switch Forward Converter

This paper addresses the common-mode (CM) electromagnetic interference noise issues in the two-switch forward converter. The two-switch forward converter has low CM noise compared to other topologies because its symmetric primary-side circuit has two out-of-phase dv/dts that cancel each other. However, parasitic capacitances of the circuit significantly affect the symmetry and degrade the noise reduction. Moreover, the secondary-side circuit of the converter is not symmetric and still contributes to the CM noise. In this paper, the parasitic capacitances of the converter are first modeled. Different transformer structures and their parasitic capacitances are characterized. A general balance technique is introduced to further reduce the CM noise of the converter. For each transformer structure, balance can be achieved with proper connection of the windings terminals and control of the parasitic capacitances to minimize the CM noise of the converter. Experimental results validated the proposed techniques.

FLC based adjustable speed drives for power quality enhancement

This study describes a new approach based on fuzzy algorithm to suppress the current harmonic contents in the output of an inverter. Inverter system using fuzzy controllers provide ride-through capability during voltage sags, reduces harmonics, improves power factor and high reliability, less electromagnetic interference noise, low common mode noise and extends output voltage range. A feasible test is implemented by building a model of three-phase impedance source inverter, which is designed and controlled on the basis of proposed considerations. It is verified from the practical point of view that these new approaches are more effective and acceptable to minimize the harmonic distortion and improves the quality of power. Due to the complex algorithm, their realization often calls for a compromise between cost and performance. The proposed optimizing strategies may be applied in variable-frequency dc-ac inverters, UPSs, and ac drives.

A Bridgeless PFC Boost Rectifier With Optimized Magnetic Utilization

The implementation of a bridgeless power factor correction (PFC) boost rectifier with low common-mode noise is presented in this paper. The proposed implementation employs a unique multiple-winding, multicore inductor to increase the utilization of the magnetic material. The operation and performance of the circuit were verified on a 750-W, universal-line experimental prototype operating at 110 kHz.

Harmonics Study and Comparison of Z-source Inverter with Traditional Inverters

This paper presents an Impedance Source Inverter for A.C electrical drives. The impedance source inverter employs a unique impedance network cable with inverter main circuit and rectifier. By controlling the shoot-through duty cycle, the z-source inverter system using MOSFETS provide ride-through capability during voltage sags, reduces line harmonics, improves power factor and high reliability, and extends output voltage range. Analysis, simulation, and experimental results will be presented to demonstrate these new features. It reduces harmonics, electromagnetic interference noise and it has low common mode noise.