Look-ahead Adder Research Articles

Approximate single precision floating point adder for low power applications

With an increasing demand for power-hungry data-intensive computing, design methodologies with low power consumption are increasingly gaining prominence in the industry. Most of the systems operate on critical and noncritical data both. An attempt to generate a precision result results in excessive power consumption and results in a slower system. For noncritical data, approximate computing circuits significantly reduce the circuit complexity and hence power consumption. In this paper, a novel approximate single precision floating point adder is proposed with an approximate mantissa adder. The mantissa adder is designed with three 8-bit full adder blocks. In this paper, a detailed mathematical background, and proposed design approach in terms of the circuit configuration and truth tables are discussed. Additionally, a concept of switching between exact computing and approximate computing is analysed considering an approximate carry look-ahead adder. The delay and power consumption for the exact operating mode and approximate operation mode considering varied window sizes is observed. Performance of the approximate computation is compared against exact computation and varied approximate computing approaches.

A New Carry Look-Ahead Adder Architecture Optimized for Speed and Energy

We introduce a new carry look-ahead adder (NCLA) architecture that employs non-uniform-size carry look-ahead adder (CLA) modules, in contrast to the conventional CLA (CCLA) architecture, which utilizes uniform-size CLA modules. We adopted two strategies for the implementation of the NCLA. Our novel approach enables improved speed and energy efficiency for the NCLA architecture compared to the CCLA architecture without incurring significant area and power penalties. Various adders were implemented to demonstrate the advantages of NCLA, ranging from the slower ripple carry adder to the widely regarded fastest parallel-prefix adder viz. the Kogge–Stone adder, and their performance metrics were compared. The 32-bit addition was used as an example, with the adders implemented using a semi-custom design method and a 28 nm CMOS standard cell library. Synthesis results show that the NCLA architecture offers substantial improvements in design metrics compared to its high-speed counterparts. Specifically, an NCLA achieved (i) a 14.7% reduction in delay and a 13.4% reduction in energy compared to an optimized CCLA, while occupying slightly more area; (ii) a 42.1% reduction in delay and a 58.3% reduction in energy compared to a conditional sum adder, with an 8% increase in the area; (iii) a 14.7% reduction in delay and a 37.7% reduction in energy compared to an optimized carry select adder, while requiring 37% less area; and (iv) a 20.2% reduction in energy and a 55.4% reduction in area compared to the Kogge–Stone adder.

An optimized design of delay-and energy-efficient Booth multiplier

Multipliers are essential computation units in virtually all computing systems, including processors and numerous AI accelerator architectures. This paper presents an optimized architecture for a Booth multiplier, targeting high performance while minimizing energy consumption and area utilization. The design optimization focuses on all three multiplier stages: partial product generation, reduction, and summation. To enhance delay and energy efficiency in the partial product generation stage, we first employed a simplified configuration comprising inverters and a sign selection unit instead of complex binary-to-two's complement circuitry. Next, to achieve further delay and area efficiency at this stage, logic optimization is applied at the partial product's generation circuitry by designing Booth encoders to remove redundant logic in multiplexers circuitry. Moreover, we introduced specialized sign compressors tailored for carry-save compression in the compression stage. Compared to conventional counterparts, these compressors offered lower power consumption and reduced critical path delay with only two XOR logic gates. Finally, in the summation stage, we proposed an optimized design segment for Carry Look-Ahead Adder for the final summation stage, designed to deliver swift throughput with minimal fan-in logic gates, even in the context of high bit-width configurations. This segment is cascaded to make a 13-bit final adder for the summation stage in the proposed design. The proposed architecture undergoes ASIC-targeted synthesis in Cadence Genus employing FreePDK CMOS 45 nm process technology. Synthesized results, along with theoretical design complexity comparison, demonstrate that the proposed design surpasses state-of-the-art 8 × 8 multiplier designs by critical metrics, including delay, power consumption, area utilization, power delay product, and area delay product.

A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic

Adders are critical to the efficiency of arithmetic circuits in battery-powered electronic devices. This study demonstrates an 8-bit CLA (carry look-ahead adder) using single-phase ANT logic to increase the computation speed and reduce the power dissipation simultaneously. The single-phase ANT has no internal loop that optimizes the efficiency of the prior ANT. Utilizing a TSMC 40-nm technology, the proposed 8-bit CLA is fabricated. It attains the highest operating frequency of 3.2 GHz and the lowest normalized PDP (power delay product) by on-silicon measurement for 20 pF load.

A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology

Multipliers are essential components within digital signal processing, arithmetic operations, and various computational tasks, making their design and optimization crucial for improving the efficiency and performance of integrated circuits. Among multiplier architectures, Vedic multipliers stand out due to their inherent efficiency and speed, derived from ancient Indian mathematical principles. This study presents a comprehensive analysis and comparison of 4-bit Vedic multiplier designs utilizing Gate Diffusion Input (GDI), Complementary Metal-Oxide-Semiconductor (CMOS), and Transmission Gate (TG) technologies, utilizing different adder architectures such as Ripple Carry Adder (RCA), and Carry Lookahead Adder (CLA), Carry Skip Adder (CSA). The objective is to explore the performance, area, and power consumption characteristics of these multipliers across different technologies and adder implementations. Each multiplier architecture is meticulously designed and optimized to leverage the unique features of the respective technology while adhering to the principles of Vedic mathematics. The designs are evaluated based on parameters such as transistor count, delay, power dissipation, and area. The results demonstrate the effectiveness of GDI technology in terms of in tems of delay, area, power and PDP when compared with other technologies. The 4-bit Vedic multiplier has been designed using 32 nm technology within Tanner EDA software tools.

16-Bit Carry Look-Ahead Adder: Design and Layout with Cadence Tools Top of Form

Abstract: The development of highly organised architecture is the primary goal of the current communication world in order to achieve high speed computation with low power consumption. The Carry Look Ahead Adder is highly efficient due to its ability to reduce the propagation time of carry bits, resulting in time savings. The implementation of a 16-Bit Carry Look Ahead Adder using the Cadence tool is carried out in our project. Logical equations for carry generation (G) and carry propagation (P) are used to create the carry and sum for the 1-bit adder. Then, using the Virtuoso schematic editor, a single bit carry is developed. After that, a fresh cell view for the carry block is made and supplied as an input for adder implementations. Next, the bit rate is increased to 4 bits. Using this 4 bit adder, 8/16 bit adder is implemented using Cadence tool. It is necessary to have a basic understanding of IC design guidelines and fabrication procedures in order to produce the layout. Within the electronic VLSI design system, the layout will go through a Design Rule Check to find any breaches

Design and analysis of all-optical carry lookahead adder using microring resonator in Z-domain

Design and analysis of all-optical carry lookahead adder using microring resonator in Z-domain

Power and Area Efficient Four-Bit Vedic Multiplier Implemented Using a Modified Five-Bit Adder with CMOS and TG Configuration

Vedic multipliers are incredibly fast, efficient, and flexible, perfect for efficiently handling tasks like signal processing. Vedic multipliers are the go-to choice for maximizing performance and efficiency in digital designs, as the existing method adders like Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA) have more delay, area and power. The project proposal presents a novel 4-bit Vedic multiplier essential to system functionality. Optimizing the balancing area and delay is necessary for improving the system as a whole. This project aims to strike this balance, significantly improving the performance of digital systems. Here, a 5-bit adder with a unique configuration is used in place of a Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA). Using CMOS & TG Configuration, all other internal structures have been created. Performance comparisons of the CMOS and TG 5-bit Adders with the adders above are shown in terms of power, latency, and area. Various adders: 5-bit Adder with CMOS & TG design, the CMOS & TG based CLA, the CSA, and the RCA, are also involved in the multiplier's adder unit selection process. The new multiplier provides the perfect answer for energy-efficient designs by combining low power consumption with small size.

A new nano-design of 16-bit carry look-ahead adder based on quantum technology

There is a requirement and a desire to develop reliable and energy-efficient circuit designs that adapt to the expanding field of low-power circuit engineering in the VLSI domain based on nanotechnology. The quantum-dot cellular automata (QCA) technology possesses the potential to supplant the conventional, complementary metal-oxide-semiconductor (CMOS) technology in low-power nano-scale applications due to its diminutive cell dimensions, dependable circuitry architecture, and robust structural integrity. On the other hand, the carry look-ahead adder (CLA) is one of the vital circuits in digital processing utilized in diverse digital applications. In addition, for the design of this essential circuit, the occupied area and the delay play the primary role because using a simple formulation can reduce the occupied area, energy consumption, and the number of gates count. In the previous structures, high delay and use of traditional technology (like CMOS) caused an increase in the number of gate counts and occupied areas. Using QCA technology, simple quantum cells, and a low delay, all the previous shortcomings can be resolved to reduce the number of gate counts and low occupied area in the CLA circuit. This paper proposes a new method that helps the propagation characteristics generate suitable signals to reduce the number of gate counts based on adders in QCA technology. Several new blocks are used to design fast binary adders. Finally, an optimal four and 16-bit CLA circuit will be proposed based on the adder circuit. Furthermore, the execution and experimentation of outcomes are carried out utilizing QCADesigner-2.0.3. The simulation-based comparison of values justified the proposed design’s accuracy and efficiency. The simulation results demonstrate that the proposed circuit has a low area and quantum cell.

High-speed and energy-efficient asynchronous carry look-ahead adder.

Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this paper presents the designs of novel asynchronous carry look-ahead adders (CLAs) viz. a standard CLA (SCLA) and a block CLA (BCLA). The proposed CLAs are monotonic, dual-rail encoded, and are realized according to return-to-zero handshake (RZH) and return-to-one handshake (ROH) protocols using a 28-nm CMOS process technology. The proposed BCLA has a slight edge over the proposed SCLA, and the proposed BCLA reports the following optimizations in design metrics such as cycle time (delay), area, and power compared to a recently presented state-of-the-art asynchronous CLA for a 32-bit addition: (i) 32.6% reduction in cycle time, 29% reduction in area, 4.3% reduction in power, and 35.5% reduction in energy for RZH, and (ii) 31.4% reduction in cycle time, 28.9% reduction in area, 4.4% reduction in power, and 34.4% reduction in energy for ROH. Also, the proposed BCLA reports reductions in cycle time and power/energy compared to many other asynchronous adders.

A New ACD-OMP Accelerator With Clustered Computing Look-Ahead

The orthogonal matching pursuit (OMP) has been widely explored to realize real-time compressed sensing (CS) reconstruction. The matrix pseudo-inverse of the least squares (LSs) is the most computationally complex operation in the OMP. Among various algorithms to realize this complex operation, the alternative Cholesky decomposition (ACD) algorithm performs the best. However, it typically involves a very long computation time due to its iterative procedure. To accelerate the ACD-OMP algorithm, a novel method called clustered computing look-ahead (CCL) is proposed. Inspired by the famous parallel carry look-ahead adder (CLA), CCL adds a propagation matrix to decouple the data dependency in ACD and then uses a clustering operator to transform the iterative computation of ACD into a pipelined and parallelized computation. This brief also proposes an efficient hardware architecture of the CCL-based ACD-OMP algorithm for CS reconstruction. The proposed algorithm is implemented on field programmable gate array (FPGA). For sparse signals with the same sparsity and length, the proposed implementation is 1.96 times faster than state-of-the-art work.

FPGA implementation of proficient Vedic multiplier architecture using hybrid carry select adder

ABSTRACT Nowadays, the application of computations and communications is needed for high performance, reduced size and lower power utilisation. The multiply and add functions are one of the frequently used operations in digital signal processing. Various types of multipliers are available in digital Various types of multipliers are available for various Signal processing applications.. Among these multipliers, Vedic multiplier is one of the most optimised multipliers used in a signal processing module. In the existing method, the Vedic multiplier is designed with conventional adders, which is having higher area utilisation, lower speed and higher power consumption. Hence, the modified Vedic multiplier is proposed to improve the speed of multiplication using hybrid technology. The partial products of the proposed multiplication are added using 2 × 2 Vedic multiplier and hybrid carry select adder (binary to excess one converter (BEC), Han-Carlson adder and Multiplexer). The critical path delays of hybrid 4 × 4 Vedic multiplier are the summation of 2 × 2 Vedic multiplier, two full adders, two multiplexers and two BECs for producing the final product. The proposed hybrid Vedic multiplier is operated at high speed with reduced size as compared to the existing multiplier techniques. The proposed hybrid Vedic multiplier is designed and simulated using Verilog HDL and implemented in Spartan 6 field-programmable gate array device. The implementation results showed that the delay of the proposed multiplier gets ameliorated as compared to array multiplication (30.84%), Wallace tree multiplication (29.52%), multiplication based on compressor (23.71%), Vedic multiplication by carry look-ahead adder (22.91%), Vedic multiplication by ripple carry adder (14.45%), revised booth multiplication (15.42%) and Vedic multiplication by Han-Carlson adder with BEC (13.95%) and hybrid multiplier (11.37%).

ALL-OPTICAL CARRY SKIP ADDER WITH THE HELP OF TERAHERTZ OPTICAL ASYMMETRIC DEMULTIPLEXER-BASED SWITCH

The terahertz optical asymmetric demultiplexer (TOAD) or semiconductor optical amplifier (SOA)-assisted Sagnac switches have been used to construct an all-optical 4-bit carry skip adder. This design aims to satisfy the high speed and accuracy requirements of modern ultrafast digital transmission. Using a combination of an all-optical multiplexer and an all-optical full adder, we describe an all-optical carry skip adder. When compared to ripple carry adder and carry look-ahead adder, carry skip adder may be employed to create a fast arithmetical processing unit. Numerical simulation is used to develop and validate this theoretical model.

Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder

The adders are the vital arithmetic operation for any arithmetic operations like multiplication, subtraction, and division. Binary number additions are performed by the digital circuit known as the adder. In VLSI (Very Large Scale Integration), the full adder is a basic component as it plays a major role in designing the integrated circuits applications. To minimize the power, various adder designs are implemented and each implemented designs undergo defined drawbacks. The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more. To overcome such issues and to obtain better performance, a novel parallel adder is proposed. The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability. This proposed novel parallel adder is attained from the carry look-ahead adder. The merits of this suggested adder are better speed, power consumption and delay, and the capability in driving. Thus designed adders are verified for different supply, delay, power, leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder (MCCA), Carry Look Ahead Adder (CLAA), Carry Select Adder (CSLA), Carry Select Adder (CSA) and other adders.

VLSI implementation of Kogge-Stone Adder for low-power applications

The adder is a vital part of the Central Processing Unit (CPU) that can perform computational operations. It is used in digital components, mainly in the design of integrated circuits. Recent decades have seen a sharp rise in demand for mobile electronics, which has increased the need for highly efficient Very Large-Scale Integration (VLSI) structures. All operations must be computed using low-power, space-efficient designs that run faster. The Kogge-Stone adder (KSA) is an extension of the carry look-ahead adder which is used for performing fast addition in high-performance computing systems. This study compares the latency, space, and energy used by the Kogge-Stone Adder after development and implementation in Xilinx Vivado using Verilog to those of the Ripple Carry Adder (RCA) and Carry Lookahead Adder (CLA). The results show that the KSA has a decrease in power consumption as well as improvements in high speed and area compaction when compared to the RCA and CLA.

Physical Design of 64-bit Multiplier and Accumulator (MAC) Unit Using Vedic Multiplier and CLA Adder

In digital signal processing, communication systems and many other applications, multiplier and accumulator units play a crucial role. This work presents an overview of 64-bit MAC Unit, where Vedic multiplier is used as multiplier unit and compared Carry select adders (CSA) and Carry look-ahead adder (CLA) which must be used for adder unit, accumulator unit consist of Parallel in parallel out (PIPO) shift registers. As a result, CLA adder to be more effective in terms of lower delay by comparing with other adders. The MAC Unit was modelled using Verilog-HDL, where its functional verification and synthesized was done using Intel Quartus Prime 21.1, which was simulated on Questa Intel FPGA 21.1. Further GDSII file was created using the cadence tool with the help of Incisive for functional simulation, Genus for synthesis and pre-layout timing analysis, and innovus for physical design. Entire study was carried out in 180nm technology from RTL-GDSII. The delay, power, area was monitored, the memory usage, Pre-Clock Tree Synthesis, Post-Clock Tree Synthesis (CTS) were noted before and after optimization of design.

Design Optimization of the 64-Bit Carry Look-Ahead Adder Based on FPGA and Verilog HDL

Design Optimization of the 64-Bit Carry Look-Ahead Adder Based on FPGA and Verilog HDL

Digital Image Blending Using Inaccurate Addition

Inaccurate computing is found to be a high-speed, low-power and energy-efficient alternative to accurate computing for error-tolerant applications. In this context, this paper analyzes the usefulness of inaccurate computing for a digital image processing application, viz. digital image blending, which has been less explored. We analyze the use of inaccurate addition for image blending used in applications such as photo editing and computer graphics. For experimentation, we considered blending two digital images using accurate and inaccurate addition separately. We considered many inaccurate addition architectures which are suitable for implementation in both FPGA and ASIC design environments to perform a comparative analysis. We found that an inaccurate addition with an optimum inaccuracy produces a similar quality of blended image as obtained using accurate addition. The quality of blended images is quantified using standard metrics such as the peak signal-to-noise ratio and the structural similarity index measure. In particular, an inaccurate adder, M-HERLOA, was found to be preferable for image blending from the combined perspectives of quality of blended image, error metrics and design metrics. We implemented the accurate and inaccurate adders corresponding to an optimum inaccuracy in FPGA and ASIC design environments. We considered a Xilinx Artix-7 FPGA for an FPGA-based implementation and a 32/28 nm CMOS standard digital cell library for an ASIC type standard cell-based implementation. The results show that, for an FPGA-based implementation, M-HERLOA enables a reduction in delay by 13%, requires 50% fewer LUTs and 49% fewer registers and consumes 24.3% less on-chip power compared to the accurate high-speed FPGA adder while yielding a blended image of good quality. For an ASIC type standard cell-based implementation, M-HERLOA enables a reduction in delay by 64.6% (24.4%), requires 43% (82.4%), less area and dissipates 63% (67.8%) less power than the accurate carry ripple adder (carry look-ahead adder).

High-Speed and Energy-Efficient Carry Look-Ahead Adder

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.

Design and Implementation of Low Power, High-Speed Configurable Approximation 8-Bit Booth Multiplier

Multimedia, machine learning and deep learning applications have a significant constraint on power consumption. A multiplier is a crucial component for many error-aware applications. An efficient approximate computing scheme is used for the error-tolerant applications due to higher accuracy in power cases. In the Booth, multiplier approximation is implemented for partial product generation and accumulations network. The significant stage of a multiplier is accumulation. In this paper, an efficient accumulation stage is suggested for the Radix-4 and 8-bit approximate Booth multiplier. The proposed accumulation multiplier has high speed, minimum area, negligible path delay and low power consumption. Compared to the Booth multiplier design with modified Booth encoding and conventional carry look-ahead adder for product generation with no other error, the proposed 8-bit multiplier design-I reduced power consumption, area and delay a maximum of 13.7%, 8.4% and 19.8%, respectively. Also, our proposed design is compared with the design of Booth multiplier with approximate Booth encoding and conventional carry look-ahead adder for product generation. The proposed 8-bit multiplier design-II reduced power consumption, area and delay by a maximum of 38.2%, 28.3% and 13.7%, respectively.