Longest Sensitizable Path Research Articles

An analytical delay model

Delay consideration has been a major issue in design and test of high performance digital circuits. The assumption of input signal change occurring only when all internal nodes are stable restricts the increase of clock frequency. It is no longer true for wave pipelining circuits. However, previous logical delay models are based on the assumption. In addition, the stable time of a robust delay test generally depends on the longest sensitizable path delay. Thus, a new delay model is desirable. This paper explores the necessity first. Then, Boolean process to analytically describe the logical and timing behavior of a digital circuit is reviewed. The concept of sensitization is redefined precisely in this paper. Based on the new concept of sensitization, an analytical delay model is introduced. As a result, many untestable delay faults under the logical delay model can be tested if the output waveforms can be sampled at more time points. The longest sensitizable path length is computed for circuit design and delay test.

Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability

Path delay fault model is the most suitable model for detecting distributed manufacturing defects which can cause delay faults. However, the number of paths in a modern design can be extremely large and the path delay testability of many practical designs is very low. In this paper we show how to resynthesize a combinational circuit in order to reduce the total number of paths in the circuit. Our results show that it is possible to obtain circuits with a significant reduction in the number of paths while not increasing area and/or delay of the longest sensitizable path in the circuit. Research on path delay testing shows that in many circuits a large portion of paths does not have a test that can guarantee detection of a delay fault. The path delay testability of a circuit would increase if the number of such paths is reduced. We show that addition of a small number of test points into the circuit can help reducing the number of such paths in the given design.

The role of long and short paths in circuit performance optimization

In this paper, we consider the problem of determining the smallest clock period for a combinational circuit. By considering both the long and short paths, we derive three independent bounds on the clock period. The first bound is the difference between the longest path delay and the shortest path delay. The other two take the functionality of the circuit into consideration and, therefore, are usually smaller than the first one. To bring in the functionality of the circuit, we make use of a new class of paths-called the shortest destabilizing paths-as well as the longest sensitizable paths. We also show that considering both the longest sensitizable path and the shortest destabilizing path together does not always give a valid bound. The bounds on the clock period can be alternatively viewed as optimization objectives. At the physical level, the complexity of optimization very much depends on the number of long and short paths present and the number of gates shared by them. We conducted preliminary experiments to study this.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An efficient delay test generation system for combinational logic circuits

An efficient delay test generation (DTEST GEN) system for combinational logic circuits is presented. In the DTEST GEN system, delay testing problems are divided into gross delay faults and small delay faults separately so that the tradeoff between the levels of delay testing effort and the confidence levels of proper system operation can be explored. Complete automatic test pattern generation (ATPG) algorithms are proposed for both gross delay faults and small delay faults. A novel timing analysis method for delay test generation which uses a conventional depth-first search technique and a novel functionality analysis technique is introduced. The functionality analysis technique examines, necessary conditions for a given delay fault to be testable and estimates the upper bound of the good circuit propagation delay of the longest sensitizable path passing through the fault site. Several benchmark results are demonstrated for both gross delay fault testing and small delay fault testing. >