Longest Prefix Matching Research Articles

PR-Trie: A Hybrid Trie with Ant Colony Optimization Based Prefix Partitioning for Memory-Efficient IPv4/IPv6 Route Lookup

Memory-efficient Internet Protocol (IP) lookup with high speed is essential to achieve link-speed packet forwarding in IP routers. The rapid growth of Internet traffic and the development of optical link technologies have made IP lookup a major performance bottleneck in core routers. In this paper, we propose a new IP route lookup architecture based on hardware called Prefix-Route Trie (PR-Trie), which supports both IPv4 and IPv6 addresses. In PR-Trie, we develop a novel structure called Overlapping Hybrid Trie (OHT) to perform fast longest-prefix-matching (LPM) based on Multibit-Trie (MT), and a hash-based level matching query used to achieve only one off-chip memory access per lookup. In addition, the proposed PR-Trie also supports fast incremental updates. Since the memory complexity in MT-based IP lookup schemes depends on the level-partitioning solution and the data structure used, we develop an optimization algorithm called Bitmap-based Prefix Partitioning Optimization (BP2O). The proposed BP2O is based on a heuristic search using Ant Colony Optimization (ACO) algorithms to optimize memory efficiency. Experimental results using real-life routing tables prove that our proposal has superior memory efficiency. Theoretical performance analyses show that PR-Trie outperforms the classical Trie-based IP lookup algorithms.

Go-to-Controller is Better: Efficient and Optimal LPM Caching with Splicing

Modern data center networks are required to support huge and complex forwarding policies as they handle the traffic of the various tenants. However, these policies cannot be stored in their entirety within the limited memory available at commodity switches. The common approach in such scenarios is to have SDN controllers manage the memory available at the switch as a fast cache, updating and changing the forwarding rules in the cache according to the workloads dynamics and the global policy at hand. Many such policies, such as Longest-prefix-match (LPM) policies, introduce dependencies between the forwarding rules. Ensuring that the cache content is always consistent with the global policy often requires the switch to store (potentially many) superfluous rules, which may lead to suboptimal performance in terms of delay and throughput. To overcome these deficiencies, previous work suggested the concept of splicing, where modified Go-to-Controller rules can be inserted into the cache to improve performance while maintaining consistency. These works focused mostly on heuristics, and it was conjectured that the problem is computationally intractable. As our main result, we show that the problem of determining the optimal set of rules, with splicing, can actually be solved efficiently by presenting a polynomial-time algorithm that produces an optimal solution, i.e., for a given cache size we find an optimal set of rules, some of which are go-to-controller, which maximize the total weight of the cache while maintaining consistency. However, such optimality comes at a cost, encompassed by the fact that our algorithm has a significantly larger running time than SoTA solutions which do not employ splicing. Therefore, we further present a heuristic exhibiting close-to-optimal performance, with significantly improved running time, matching that of the best algorithm, which does not employ splicing. In addition, we present the results of an evaluation study that compares the performance of our solutions with that of SoTA approaches, showing that splicing can reduce the cache miss ratio by as much as 30%, without increasing the cache size. Lastly, we propose a simple and fast-to-compute metric (that is consistency-oblivious) in order to evaluate the potential benefits of splicing compared to classical LPM-caching, for a given policy and traffic distribution. We show that our metric is highly correlated with such benefits, thus serving as an indication of whether splicing should be incorporated within the system architecture.

Duo: A High-Throughput Reconfigurable Datacenter Network Using Local Routing and Control

The performance of many cloud-based applications critically depends on the capacity of the underlying datacenter network. A particularly innovative approach to improve the throughput in datacenters is enabled by emerging optical technologies, which allow to dynamically adjust the physical network topology, both in an oblivious or demand-aware manner. However, such topology engineering, i.e., the operation and control of dynamic datacenter networks, is considered complex and currently comes with restrictions and overheads. We present Duo, a novel demand-aware reconfigurable rack-to-rack datacenter network design realized with a simple and efficient control plane. Duo is based on the well-known de Bruijn topology (implemented using a small number of optical circuit switches) and the key observation that this topology can be enhanced using dynamic (''opportunistic'') links between its nodes. In contrast to previous systems, Duo has several desired features: i) It makes effective use of the network capacity by supporting integrated and multi-hop routing (paths that combine both static and dynamic links). ii) It uses a work-conserving queue scheduling which enables out-of-the-box TCP support. iii) Duo employs greedy routing that is implemented using standard IP longest prefix match with small forwarding tables. And iv) during topological reconfigurations, routing tables require only local updates, making this approach ideal for dynamic networks. We evaluate Duo in end-to-end packet-level simulations, comparing it to the state-of-the-art static and dynamic networks designs. We show that Duo provides higher throughput, shorter paths, lower flow completion times for high priority flows, and minimal packet reordering, all using existing network and transport layer protocols. We also report on a proof-of-concept implementation of Duo's control and data plane.

LPR-Trie: A fast IPv6 routing lookup algorithm with virtual nodes

The number of IPv6 routes in todays backbone routers has grown rapidly, which has put tremendous pressure on route lookup and storage. Based on the analysis of IPv6 address prefix length and distribution characteristics, this paper proposes an IPv6 route lookup architecture called LPR-Trie. The core idea of the algorithm is to utilize more spaces and accelerate routing lookup. Moreover, we put forward the concept of virtual nodes, and leverage the link between virtual nodes and ordinary nodes to accelerate routing lookup. We provide the longest prefix routing entry (LPR) calculation algorithm to achieve the longest prefix match. The experimental results show that the virtual node mechanism increases the search speed up to 244%, and the virtual nodes have better stability by setting an appropriate keep-alive time according to the characteristics of actual traffic. This paper shows that our design improves the routing lookup speed and have better memory utilization.

Filter‐Sketch: A two‐layer sketch for entropy estimation in the data plane

Entropy-based approaches have been shown to aid various network measurement applications such as load balancing, anomaly detection, and traffic classification. Existing methods that assume out-of-band detection and/or use switches merely as accelerators require frequency communication between data and control plane, which increase the burden on the network and are no longer sufficient. To track these challenges, the authors design and implement a switch-native approach for entropy estimation that can run detection function entirely inline on data plane. The authors first present Filter-Sketch, a two-layer sketch that supports frequency estimation with small and static memory allocation by separating elephant flow and mice flow. Then, the authors propose a mechanism based on memory-optimized longest-prefix match (LPM) to attain entropy at a line rate that completely executes in the programmable data plane. The trace-driven evaluation shows that Filter-Sketch achieves higher accuracy than the existing data plane algorithm in entropy estimation, where the relative error decreases by 0.65 on average.

Scalable name identifier lookup for Industrial Internet

Name identifiers are considered more effective than IP addresses in routing and forwarding billions of heterogeneous resource-restrained Industrial Internet objects. Although the design of name-based longest prefix matching lookup has been developed for nearly a decade, it is still attractive to design an efficient name lookup scheme for the Industrial Internet due to hierarchical variable-length names, large-scale forwarding tables, and frequent updates. In this paper, we present a memory-optimized binary search (MOBS) algorithm in the counting Bloom filter (CBF), which decreases memory consumption by reducing the storage of prefix marker entries while maintaining the fast lookup efficiency of binary search. Furthermore, we propose CBF-HT, an efficient and scalable name lookup method that combines counting Bloom filter and hash table to facilitate content forwarding. CBF-HT consists of two stages. Firstly, the longest prefix matching results are obtained through binary search in the counting Bloom filter with MOBS, and then the final lookup results are acquired by linear backtracking in the hash table. CBF-HT can achieve high-speed lookups and fast updates, and significantly reduces memory consumption caused by marker entries through MOBS. We have implemented and evaluated CBF-HT with 10 billion name identifiers. Experimental results show that, compared with the existing binary search on hash table algorithm (BS-HT), CBF-HT increases the forwarding throughput by 45%, eliminates 73% and 90% of memory consumption, and improves the update performance by 48.1%, at the cost of a 7.8% increase in the average number of memory accesses.

Surgical DDoS Filtering With Fast LPM

Can software-based packet filters effectively dampen volumetric distributed denial-of-service (DDoS) streams in an era when 10 Gbps links are considered slow? The potential of longest prefix matching (LPM) for enforcing precise DDoS scrubbing policies seems to be overlooked in contemporary packet filtering datapaths, and in this paper, we argue that this should not be the case by showing that effective whitelist / blacklist LPM-based filtering can be performed with commodity hardware. A showcase datapath we propose can evaluate multiple queries in large separate LPM databases for each forwarded 64-byte packet, while sustaining 10 Gbps line rate on a single CPU core, with a healthy scaling potential due to its lockless architecture and small memory footprint of LPM structures. We demonstrated forwarding 64 million packets per second using only six CPU cores while performing independent lookups for each packet in three large LPM databases created by aggregating malicious IP addresses or by mapping different geolocation identifiers to IPv4 prefixes.

A minimal resource high‐speed routing lookup mechanism for servers with NetFPGAs

AbstractThis paper studies how high‐performance computer servers, equipped with Field‐Programmable Gate Arrays (FPGAs), can perform high‐speed routing. In particular, routing table lookup is considered since it is a key packet processing bottleneck for future routers that need to operate at Petabits‐per‐second. The paper defines and evaluates three routing lookup schemes used by routers/switches, using Xilinx NetFPGA SUME programmable data plane hardware boards. Two existing schemes, namely IP address‐based Longest Prefix Matching and Multi‐Protocol Label Switching tag‐based exact matching are implemented. In addition, the paper presents a new routing scheme called No Lookup Forwarding Scheme (NLFS) that does not use conventional lookup tables. The NLFS approach adds a custom routing tag that does not require any form of (forwarding) table lookup, and independent of the Binary/Ternary Content Associate Memory (CAM) capacity in the switch/router. The experimental results show that the NLFS scheme utilizes less FPGA resources, while reducing packet lookup latency by up to 18% against longest prefix match which is the de facto lookup mechanism used in switches. The key contribution of this work is that it enables the use of NetFPGAs to reduce CAM capacity requirements in switches/routers to help reduce memory costs. The proposed scheme has several use cases, including provision of on‐demand increase of packet routing capacity in data center networks and support for Network Function Virtualization‐based systems.

On the Prefix Granularity Problem in NDN Adaptive Forwarding

One unique architectural benefit of Named Data Networking (NDN) is adaptive forwarding, i.e., the forwarding plane is able to observe past data retrieval performance and use it to adjust forwarding decisions for future Interests. To be effective, adaptive forwarding assumes that <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Interest Routing Locality</i> is related to Interests’ common name prefix, meaning that Interests sharing the same prefix are likely to follow a similar forwarding path within a short period of time. Since Interests can have multiple common prefixes with different lengths, the real challenge is determining which prefix length should be used in adaptive forwarding to record path performance measurements - we refer to this as the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Prefix Granularity Problem</i> . The longer the common prefix is, the better the Interest Routing Locality, and the larger the forwarding table. Given the limited FIB size, route names are designed to be considerably shorter than Interest names. Existing adaptive forwarding designs use route names to record path performance measurements, which looses forwarding adaptability as it promises in the event of partial network failures. In this work, we propose to dynamically aggregate and de-aggregate name prefixes in the forwarding table in order to use the prefixes that are the most appropriate given current network situation. In addition, to reduce the overhead of adaptive forwarding, we propose mechanisms to minimize the use of the longest prefix matching in Data packet processing. Simulations demonstrate that the proposed techniques can result in better forwarding decisions in the event of partial network failures with significantly reduced overhead.

Using XorOffsetTrie for high-performance IPv6 lookup in the backbone network

The development of IPv6 in scale and traffic requires the IPv6 lookup algorithm to perform fast longest prefix matching (LPM), especially in the backbone network. However, existing IPv6 lookup algorithms, e.g., SAIL, Poptrie, and Hi-BST have limited lookup speeds with too many memory accesses. To achieve the highest lookup speed with fewer memory accesses, we propose the XorOffsetTrie method, which is the combination of XorFilter and OffsetTrie. OffsetTrie reduces the memory accesses by combining the offset index and the next hop of rule into an integer. XorFilter further improves lookup speed by matching about 63% rules with one memory access. If a packet matches a rule in XorFilter, we can return the next hop of this rule immediately. Otherwise, we continue to lookup in OffsetTrie. With high efficient data structure for lookup process, the lookup speed of XorOffsetTrie achieves 1.6x, 4.2x, 8.5x that of SAIL, Poptrie, and Hi-BST.

Approximate Packet Classifiers With Controlled Accuracy

Performing exact computations can require significant resources. Approximate computing allows to alleviate resource constraints, sacrificing the accuracy of results. In this work, we consider a generalization of the classical packet classification problem. Our major contribution is to introduce representations of approximate packet classifiers with controlled accuracy and optimization techniques to reduce classifier sizes exploiting this new level of flexibility. In this work, we propose methods constructing efficient approximate representations for both LPM (longest prefix match) classifiers and classifiers with general ternary-bit filters. We validate our theoretical results with a comprehensive evaluation study showing that a small error in the actions of a classifier can lead to significant memory reductions, often comparable to the best possible theoretical reduction in the trivial case when all rules have the same action.

Feasibility of Longest Prefix Matching using Learned Index Structures

This paper revisits longest prefix matching in IP packet forwarding because an emerging data structure, learned index, is recently presented. A learned index uses machine learning to associate key-value pairs in a key-value store. The fundamental idea to apply a learned index to an FIB is to simplify the complex longest prefix matching operation to a nearest address search operation. The size of the proposed FIB is less than half of an existing trie-based FIB while it achieves the computation speed nearly equal to the trie-based FIB. Moreover, the computation speed of the proposal is independent of the length of IP prefixes, unlike trie-based FIBs.

A self-stabilizing Hashed Patricia Trie

While many research in distributed computing has covered solutions for self-stabilizing computing and topologies, there is far less work on self-stabilization for distributed data structures. However, when peers in peer-to-peer networks crash, a distributed data structure may not remain intact. We present a self-stabilizing protocol for a distributed data structure called the Hashed Patricia Trie (Kniesburges and Scheideler WALCOM'11) that enables efficient prefix search on a set of keys. The data structure has many applications while offering low overhead and efficient operations when embedded on top of a Distributed Hash Table. Especially, longest prefix matching for x can be done in O(log⁡|x|) hash table read accesses. We show how to maintain the structure in a self-stabilizing way, while assuring a low overhead in a legal state and an asymptotically optimal memory demand of Θ(d) bits, where d is the number of bits needed for storing all keys.

Memory Efficient Hash-Based Longest Prefix Matching Architecture with Zero False +ve and Nearly Zero False -ve Rate for IP Processing

A novel hash-based hardware architecture for longest prefix match (LPM) scheme has been presented for IP processing.The main idea is to have zero false positive (+ve) rate with negligible false negative (-ve) rate. This has been achieved by implementing hardware-based simple hash functions for faster generation of routing table addresses. Prefix table has been designed using multiple read-port memory modules to deploy concurrent access of multiple memory words. Moreover, in this architecture, memory requirement has been reduced by maintaining next-hop address pointers instead of keeping actual next-hop address using global next-hop address memory. Prefix search time is fixed and restricts an LPM search operation within a single clock cycle irrespective of IPv4 and IPv6 address suits. This architecture can accommodate increased prefix growth trend of 40% – 100% with unchanged memory capacity. After rigorous testing, false -ve rate is found mostly zero and reasonably negligible (0.00512%) in worst-cases, however, false +ve rate is always zero. Lower bounds in memory requirements for four numerous schemes of the proposed LPM architecture with their probable failure-rates are analysed. System failure-rates are observed against incremental prefix growth with variable number of hash functions ranging from 6 to 8 to ensure future sustainability of the scheme.

A Novel Prefix Cache with Two-Level Bloom Filters in IP Address Lookup

Prefix caching is one of the notable techniques in enhancing the IP address lookup performance which is crucial in packet forwarding. A cached prefix can match a range of IP addresses, so prefix caching leads to a higher cache hit ratio than IP address caching. However, prefix caching has an issue to be resolved. When a prefix is matched in a cache, the prefix cannot be the result without assuring that there is no longer descendant prefix of the matching prefix which is not cached yet. This is due to the aspect of the IP address lookup seeking to find the longest matching prefix. Some prefix expansion techniques avoid the problem, but the expanded prefixes occupy more entries as well as cover a smaller range of IP addresses. This paper proposes a novel prefix caching scheme in which the original prefix can be cached without expansion. In this scheme, for each prefix, a Bloom filter is constructed to be used for testing if there is any matchable descendant. The false positive ratio of a Bloom filter generally grows as the number of elements contained in the filter increases. We devise an elaborate two-level Bloom filter scheme which adjusts the filter size at each level, to reduce the false positive ratio, according to the number of contained elements. The experimental result shows that the proposed scheme achieves a very low cache miss ratio without increasing the number of prefixes. In addition, most of the filter assertions are negative, which means the proposed prefix cache effectively hits the matching prefix using the filter.

FCTrees: A Front-Coded Family of Compressed Tree-Based FIB Structures for NDN Routers

Named data networking (NDN) is a nascent vision for the future Internet that replaces IP addresses with content names searchable at the network layer. One challenging task for NDN routers is to manage huge forwarding information bases (FIBs) that store next-hop routes to contents. In this article, we propose a family of compressed FIB data structures that significantly reduce the required storage space within the NDN routers. Our first compressed FIB data structure is FCTree. FCTree employs a localized front-coding compression, that eliminates repeated prefixes, to buckets containing partitions of routes. These buckets are then organized in self-balancing trees to speed up the longest prefix match (LPM) operations. We propose two enhancements to FCTree, a statistically compressed FCTree (StFCTree) and a dictionary compressed FCTree (DiFCTree). Both StFCTree and DiFCTree achieve higher compression ratios for NDN FIBs and can be used for FIB updates or exchanges between the forwarding and control planes. Finally, we provide the control plane with several knobs that can be employed to achieve different target trade-offs between the lookup speed and the FIB size in each of these structures. Theoretical analysis along with experimental results demonstrate the significant space savings and performance achieved by the proposed schemes.

Route Prefix Caching Using Bloom Filters in Named Data Networking

This paper proposes an elaborate route prefix caching scheme for fast packet forwarding in named data networking (NDN) which is a next-generation Internet structure. The name lookup is a crucial function of the NDN router, which delivers a packet based on its name rather than IP address. It carries out a complex process to find the longest matching prefix for the content name. Even the size of a name prefix is variable and unbounded; thus, the name lookup is to be more complicated and time-consuming. The name lookup can be sped up by using route prefix caching, but it may cause a problem when non-leaf prefixes are cached. The proposed prefix caching scheme can cache non-leaf prefixes, as well as leaf prefixes, without incurring any problem. For this purpose, a Bloom filter is kept for each prefix. The Bloom filter, which is widely used for checking membership, is utilized to indicate the branch information of a non-leaf prefix. The experimental result shows that the proposed caching scheme achieves a much higher hit ratio than other caching schemes. Furthermore, how much the parameters of the Bloom filter affect the cache miss count is quantitatively evaluated. The best performance can be achieved with merely 8-bit Bloom filters and two hash functions.

Fast Longest Prefix Matching by Exploiting SIMD Instructions

Longest prefix matching (LPM) is a fundamental process in IP routing used not only in traditional hardware routers but also in software middleboxes. However, the performance of LPM in software is still insufficient for processing packets at over 100 Gbps, although previous studies have tackled this issue by exploiting the CPU cache or accelerators such as GPUs. To improve the performance of software LPM further, we propose a novel LPM method called Spider, which exploits a single-instruction multiple-data (SIMD) mechanism in the CPU. Spider achieves performing LPM for up to 16 destination IP address in parallel by a routing table structure carefully designed for processing by the SIMD instructions. We evaluated Spider from the following three perspectives: the improvement of LPM performance derived from the parallelism provided by the SIMD mechanism, performance comparison with other methods, and performance scalability. The evaluation shows that Spider dramatically improves the LPM performance, which reaches 1.8-3.2 times compared with the state-of-the-art methods. Moreover, Spider achieves 5,074 million lookups per second with 16 CPU cores, which is equivalent to the processing capacity of 3.4 Tbps in short packets; the performance opens up the possibility of packet processing at the terabit-class rate by software.

Efficient Lookup Solutions for Named Data Networks

Named Data Networking (NDN) is afast growing architecture, which is proposed as an alternative to existing IP. NDN allows users to request the data identified by a unique name without any information of the hosting entity. NDN supports in-network caching of contents, multi-path forwarding, and data security. In NDN, packet-forwarding decisions are driven by lookup operations on content name of the NDN packets. An NDN node maintains set of routing tables that aid in forwarding decisions. Forwarding the NDN packets depend on lookup of these NDN tables and performing Longest Prefix Matching (LPM) against these NDN tables. The NDN names are unbounded and of variable length. These features along with large and dynamic NDN tables pose several challenges that include increased memory requirement and delayed lookup operations. To this end, there is a need for an efficient data structure that support fast lookup operations with low memory overhead. Several lookup techniques are proposed in this direction. Traversing trie structures would be slow since every level of trie require a memory access. Hash tables incur additional hash computations on names and suffer from collisions. Bloom filters suffer from false positives and do not support deletions. Improving the performance of these structures can lead to a better lookup solution.This survey paper explores different lookup structures for NDN networks. Performance is measured with respect to lookup rate and memory efficiency.

VeriTable: Fast equivalence verification of multiple large forwarding tables

Due to network practices such as traffic engineering and multi-homing, the number of routes, also known as IP prefixes, in the global forwarding tables has been increasing significantly in the last decade and continues growing in a super linear trend. One of the most promising solutions is to use Forwarding Information Base (FIB) aggregation algorithms with incremental handling of BGP updates. FIB aggregation compresses the forwarding tables by reducing the number of prefixes in an FIB. Obviously, FIB aggregation should preserve the forwarding behavior of the data plane, i.e., packets must be forwarded in the same directions as if the original FIB is applied. Failures at the control plane or an incorrect algorithm may violate this rule. Thus we pose a research question, how can we efficiently verify that the original table achieves the same forwarding behavior for a router as the aggregated one? This paper proposes VeriTable, an algorithm that addresses the problem of verification of the equivalence of forwarding tables and the challenges caused by the Longest Prefix Matching (LPM) lookups. VeriTable employs a single tree traversal to quickly check if multiple forwarding tables are equivalent, as well as if they result in network ”black-holes”. VeriTable algorithm significantly outperforms the state-of-the-art work for both IPv4 and IPv6 tables in terms of the total running time, memory access times and memory consumption.