Logical Zeros Research Articles

The determination of redundant test patterns based on binary matrix symmetry properties

The object of research are digital circuit control tests. The model of a digital circuit is of a grey-box type. Test patterns (impacts) are combinations of logical zeros and ones, applied to circuit inputs. A binary matrix is the response of a digital circuit to input impacts. The examined faults are of «bridging faults» and «stuck-at faults» types. We distinguish the structural units of a test, as well as transformations, maintaining its structure. The measure of binary matrix symmetry is defined. Based on the measure obtained, the criteria are introduced, which help to calculate the utility of another test impact upon a digital circuit. To investigate the criteria, both pseudo-random and deterministic test sequences have been used. Among others, we have observed such algorithmic sequences as a sliding-ONE test, a logarithmic test, a galloping test pattern and a checkerboard test. The proposed approach gives the possibility to identify and exclude the impacts, not carrying useful information, from a test of combinational circuit control. The developed criteria can also be applied to construct memory tests. The analysis of experimental data allows us to make a conclusion about the advisability of using the proposed mathematical apparatus in the theory and practice of digital device testing, as well as in processes of test development.

Conflux—An Asynchronous Two-to-One Multiplexor for Time-Division Multiplexing and Clockless, Tokenless Readout

This article describes an independent, self-arbitrating asynchronous two-to-one multiplexor called Conflux. Conflux can be used to implement clockless and tokenless time-division multiplexing between two sources. This capability can then be used to create a clockless and tokenless aggregate data bus that can be used as a complete asynchronous readout architecture for a chip, a part of a chip, or an entire multichip system. Conflux utilizes a classic, four-phased asynchronous handshake on both of its input ports as well as on its output port. Asynchronous Request is bundled with Data to ensure consistent propagation delay. The Request is also implemented as a differential signal to account for propagation delay differences between logical ones and zeros. Arbitration between the two Conflux input streams is accomplished by three Set–Reset Latches. Finally, Conflux cells were used successfully to implement the readout architecture of the FCP130 prototype chip. Tests indicate single Conflux stage delays of 1.8 ns and a bandwidth of approximately 11 Gb/s in 130-nm CMOS.

Large signal-to-noise-ratio enhancement of ultrashort pulsed optical signals using a power-symmetric Nonlinear Optical Loop Mirror with output polarisation selection

A numerical study of a fibre-based scheme for the regeneration of ultrashort-pulsed optical signals is presented. The setup is made of a power-symmetric Nonlinear Optical Loop Mirror (NOLM) followed by a polariser. The NOLM operates through nonlinear polarisation rotation, and includes twisted, anomalous-dispersion fibre and a quarter-wave retarder. When the orientations of the linear input polarisation and of the output polariser are properly adjusted, the output energy characteristic flattens at high power, a property that can be used to eliminate large amplitude fluctuations on the logical ones of an optical signal. When the input pulse parameters closely match those of fundamental solitons or of stable elliptically polarised solitary waves, a wide and flat plateau is obtained, allowing the reduction of ∼30% amplitude fluctuations to less than 1%. Very large amplitude fluctuations beyond 50% can also be reduced down to a few %. Although the output pulses are slightly chirped, they are free of pedestal, thanks to the zero low-power transmission of the NOLM, which also allows the simultaneous regeneration of logical zeros. We believe that this setup will be useful for the regeneration of highly degraded signals in future ultrafast transmission networks.

Communication Links for Distributed Quantum Computation

Distributed quantum computation requires quantum operations that act over a distance on error correction-encoded states of logical qubits, such as the transfer of qubits via teleportation. We evaluate the performance of several quantum error correction (QEC) codes and find that teleportation failure rates of one percent or more are tolerable when two levels of the [[23, 1, 7]] code are used. We present an analysis of performing QEC on QEC-encoded states that span two quantum computers, including the creation of distributed logical zeros. The transfer of the individual qubits of a logical state may be multiplexed in time or space, moving serially across a single link or in parallel across multiple links. We show that the performance and reliability penalty for using serial links is small for a broad range of physical parameters, making serial links preferable for a large, distributed quantum multicomputer when engineering difficulties are considered. Such a multicomputer will be able to factor a 1,024-bit number using Shor's algorithm with a high probability of success.

Bit-error-ratio improvement with 2R optical regenerators

We show that an all-optical optical regenerator can improve the bit-error ratio (BER) of a signal passing through it only if the regenerator has different power transfer functions for the logical ones and logical zeros. A regenerator that operates with a single transfer function-which constitute most of optical regenerators reported in the literature-cannot improve the BER, but can only reduce the BER degradation when, for example, placed before optical amplifiers. Of all the optical regenerators reported to date, only the one proposed by Mamyshev, based on filtering a self-phase modulated signal, has different transfer functions for the logical ones and the logical zeros. This makes the Mamyshev scheme a superior candidate for ultrahigh-speed all-optical regeneration.

Calculation of bit-error probability for a lightwave system with optical amplifiers and post-detection Gaussian noise

The author's previously published results (ibid., vol.8, p.1816-23, 1990) which dealt with the bit-error probability of a lightwave communication system whose noise contribution was exclusively attributed to spontaneous emission noise of optical amplifiers are extended. The earlier theory was based on an NRZ (nonreturn-to-zero) modulation format with zero signal power assigned to logical zeros. The extension is based on the same mathematical technique but includes Gaussian noise originating after the signal has been converted to an electrical current. This noise could be thermal noise, shot noise, or a combination of both. It is no longer assumed that the pulse representing a logical one fills its time slot completely. Now, the optical pulses can be much shorter than the bit period (solitons), the power level of logical zeros need not vanish, and the thermal noise of the postdetection electronic circuit is taken into account. >

A 34-ns 1-Mbit CMOS SRAM using triple polysilicon

A 128-kb word/spl times/8-b CMOS SRAM with an access time of 3 ns and a standby current of 2 /spl mu/A is described. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS technology with 0.8-/spl mu/m minimum design features. A high-resistive third polysilicon load has been developed to realize a low standby current. In order to obtain a faster access time, a 16-block architecture and a data-output presetting technique combined with address transition detection (ATD) are used. This RAM has a flash-clear function in which logical zeros are written into all memory cells in less than 1 /spl mu/s.

Wall coding for field access bubble device

We report results of wall state coding in a field access device. The wall states chosen to be logical ones and zeros are S=1 and S= ½ states, both of which have unsaturated capping layers. The 2.7 μm epi garnet (YSm Gd CaGe) is grown on top of a thin (.2 μm) epi garnet (Y Nd CaGe) layer with in-plane magnetization, called a boot. With the capping in-plane layer placed below the bubble film, the stability of the wall states is considerably enhanced against an upper cap switch ( S=1 \rightarrow S=0 ) caused by the fringe field of the permalloy. The device has a nucleator and chevron shift register which feeds into a current-access deflectometer where bubble wall states are differentiated by their deflection angle. After differentiation, S=1 bubbles go to a guard rail and S= ½ bubbles are sent to a chevron expander and detector. The bubbles are coded by applying current pulses to conductors which are placed adjacent to the shift register. The coder geometries will be described. Generally, a ½ state is made by supplying an in-plane field which adds to the external in-plane field and causes an upper cap switch, making an S=0 bubble. The lower cap switch is ∼80 Oe and the S=0 bubble decays to the S= ½ (logical zero) in the 50 Oe drive field. An S=1 state is formed by applying current such that an in-plane field subtracts from the external drive field causing the S= ½ \rightarrow S=1 transition by Bloch line annihilation. Coding margins of current, phase and bias have been taken for both states. We find that the margins are almost constant over the bias range of the deflectometer, which is 17 Oe. For ½ coding, the phase margin is 30° with a current margin of about 40%. The margins for coding the S=1 state are somewhat narrower with phase \sim25\deg and current 20%.

The light-sensitive MNOS memory transistor

In a simple memory application the threshold voltage V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> of an MNOS transistor is switched by means of write and erase pulses of opposite polarities between two levels, representing logical ONEs and ZEROs. It is shown that by isolating the source and drain during the write pulse, the magnitude of the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> shift can be made dependent on the intensity of light on the MNOS device. By choosing the light intensity and the width of the write pulse properly, the device can be made to operate in either a digital or analog mode. The theory of this effect, applicable to both transistors and capacitors, is developed by generalizing the well-understood behavior of the MNOS memory device to include conduction in the silicon space-charge region. The operation of the device depends on the current-field relationships for the nitride, oxide, and silicon space-charge layers. It is shown how these three functions may be obtained from steady-state I-V measurements on the MNOS device. Good agreement is found between experimental and calculated charging curves for both transistors and capacitors.