Logical Neighborhood Research Articles

Design and reliability analysis of fault-tolerant shuffle exchange gamma logical neighborhood interconnection network

Multistage interconnection networks are used as a medium for interconnecting processors and memories in multiprocessor systems. Multistage interconnection networks are an effective substitute for crossbar switches, used in telephone network systems and parallel computers, due to their low cost, better performance and easy maintainability. In this paper, we propose new fault-tolerant hybrid multistage interconnection networks obtained from shuffle exchange gamma interconnection network (SEGIN) and logical neighborhood network named as shuffle exchange gamma logical neighborhood interconnection network (SEGLNIN). We evaluated the performance of SEGLNIN in terms of disjoint paths, reliability and hardware cost and compared it with some well-known MINs like shuffle exchange network (SEN), shuffle exchange network with one extra stage (SEN +) and shuffle exchange network with two extra stages (SEN + 2), SEGIN-1, and SEGIN-2. The results illustrate that the performance of the proposed SEGLNIN is better than that of the compared networks in terms of reliability and disjoint paths.

Information extraction from sensor networks using the Watershed transform algorithm

Wireless sensor networks are an effective tool to provide fine resolution monitoring of the physical environment. Sensors generate continuous streams of data, which leads to several computational challenges. As sensor nodes become increasingly active devices, with more processing and communication resources, various methods of distributed data processing and sharing become feasible. The challenge is to extract information from the gathered sensory data with a specified level of accuracy in a timely and power-efficient approach. This paper presents a new solution to distributed information extraction that makes use of the morphological Watershed algorithm. The Watershed algorithm dynamically groups sensor nodes into homogeneous network segments with respect to their topological relationships and their sensing-states. This setting allows network programmers to manipulate groups of spatially distributed data streams instead of individual nodes. This is achieved by using network segments as programming abstractions on which various query processes can be executed. Aiming at this purpose, we present a reformulation of the global Watershed algorithm. The modified Watershed algorithm is fully asynchronous, where sensor nodes can autonomously process their local data in parallel and in collaboration with neighbouring nodes. Experimental evaluation shows that the presented solution is able to considerably reduce query resolution cost without scarifying the quality of the returned results. When compared to similar purpose schemes, such as “Logical Neighborhood”, the proposed approach reduces the total query resolution overhead by up to 57.5%, reduces the number of nodes involved in query resolution by up to 59%, and reduces the setup convergence time by up to 65.1%.

Reasoning for Web document associations and its applications in site map construction

Recently, there is an interest in using associations between Web pages in providing users with pages relevant to what they are currently viewing. We believe that, to enable intelligent decisions, we need to answer the question “for a given set of pages, find out why they are associated”. We present a framework for reasoning about Web document associations. We start from the observation that the reasons of the Web page associations are implicitly embedded in the content of the pages as well as the links connecting them. The association reasoning scheme we propose is based on a random walk algorithm. This algorithm can take both link structure and contents into consideration and allows users to specify a focus. We then show how the proposed algorithm, combined with a logical domain identification technique, can be used for Web site summarization and Web site map construction to help users navigate through complex corporate sites. We see that, to achieve this goal, it is essential to recover the Web authors' intentions and superimpose it with the users' retrieval contexts in summarizing Web sites. Therefore, we present a framework, which uses logical neighborhoods, entry pages, and associations of entry pages, in creating context-sensitive summaries and maps of complex Web sites.

Doing well enough: Toward a logic for common-sense morality

On the traditional deontic framework, what is required (what morality demands) and what is optimal (what morality recommends) can't be distinguished and hence they can't both be represented. Although the morally optional can be represented, the supererogatory (exceeding morality's demands), one of its proper subclasses, cannot be. The morally indifferent, another proper subclass of the optional-one obviously disjoint from the supererogatory-is also not representable. Ditto for the permissibly suboptimal and the morally significant. Finally, the minimum that morality allows finds no place in the traditional scheme. With a focus on the question, “What would constitute a hospitable logical neighborhood for the concept of supererogation?”, I present and motivate an enriched logical and semantic framework for representing all these concepts of common sense morality.

Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults

State-of-the-art RAM chips are designed with spare rows and columns for reconfiguration purposes. After a RAM chip is reconfigured, physically adjacent spare cells may no longer have consecutive logical addresses. Another aspect that results in distinct logical and physical neighborhoods in RAM's is the scrambling of address lines, necessitated by the need to minimize the overall silicon area and the critical path lengths. Test algorithms used to test reconfigured RAM's and scrambled address RAM's for the detection of physical neighborhood pattern sensitive faults have to consider that the physical and logical neighborhoods are different and that the address mapping of the reconfigured RAM is no longer available. In this paper, we present a test algorithm that detects static five-cell physical neighborhood pattern sensitive faults in reconfigured RAMs and RAMs with scrambled address lines. This algorithm is based on the widely used MSCAN and Marching test algorithms, and requires only O(N[log/sub 2/N]) reads and writes to test an N-bit RAM array.

Optical parallel array logic system 2: A new system architecture without memory elements

An optical parallel array logic system—OPALS—is a new type of optical parallel digital computing system. The OPALS optically implements array logic in parallel using techniques of image coding and 2-D correlation for the coded image with a pointwise function called an operation kernel. The OPALS can execute any logical neighborhood operation for binary images in parallel. In this paper we present a new version of the OPALS that needs no memory elements. To construct this OPALS, we consider two useful techniques, i.e., an optical sequential logic technique and multiplex correlation based on wavelength multiplexing. Use of pipelined processing together with the wavelength multiplexing technique gives the promise of eliminating memory devices from the system. Consequently, the new version of the OPALS can be systematized with simpler architecture compared with that of the OPALS presented in the previous paper. Computer simulation verifies the appropriateness of operations of the new version of the OPALS.

A Dedicated Processor for Low-Level Vision

Abstract A microprogrammable processor for low-level vision has been developed. It can be used as a slave processor in Multibus-based vision systems. The architecture of the processor is designed to be efficient in binary image analysis and in many common gray scale operations. The implemented operations include connectivity analysis and logical neighborhood operations for binary images, pixel operations, convolutions and geometric transformations for gray scale images and arithmetic and logical operations between two images. Typical execution times of operations vary from 50 ms to 500 ms for a 256 by 256 pixel image depending on the complexity of the operation. The processor is implemented in three boards with standard MSI and LSI technology. Potential applications for the processor are in industrial automation, graphics arts industry and medicine.

Digital extraction of interference fringe contours

Two basic techniques for extracting interferogram contours have been discussed. The first is a global contour extracton technique based on the fast Fourier transform. The second extracts individual contours with a thinning algorithm using logical neighborhood transformations. (AIP)