Logical Address Research Articles

Optimizing Garbage Collection for ZNS SSDs via In-storage Data Migration and Address Remapping

The NVMe Zoned Namespace (ZNS) is a high-performance interface for flash-based solid-state drives (SSDs), which divides the logical address space into fixed-size and sequential-write zones. Meanwhile, ZNS SSDs eliminate in-device garbage collection (GC) by shifting the responsibility of GC to the host. However, the host-side GC of ZNS SSDs is not efficient. On the one hand, data migration during GC first moves data to the host buffer and then writes back the transferred data to the new location in the SSD, resulting in an unnecessary end-to-end transfer overhead. On the other hand, due to the pre-configured mapping between zones and blocks, GC incurs a large block-to-block rewrite overhead, i.e., even if most of the data in a block of the victim zone is valid, the valid data will still be rewritten to another block in the target zone. To address these issues, this paper proposes a novel ZNS SSD design that features dynamic zone mapping, termed Brick-ZNS . Brick-ZNS implements two key functionalities: in-storage data migration and address remapping. New ZNS commands are first designed to realize in-storage data migration to avoid the end-to-end transfer overhead of GC while ensuring performance predictability. Then, a remapping strategy exploiting parallel physical blocks is proposed to reduce the large block-to-block rewrite overhead while ensuring zone-level access parallelism. The basic idea of the strategy is to directly remap the parallel physical blocks with a sufficient amount of valid data in the victim zone to the target zone, hence avoiding the large block-to-block rewrite overhead. Based on a full-stack SSD emulator, the evaluation results show that Brick-ZNS improves write throughput by 25% and SSD lifetime by 1.41 ×.

Fair-ZNS: Enhancing Fairness in ZNS SSDs Through Self-Balancing I/O Scheduling

The NVMe Zoned Namespace (ZNS) is a new type of storage interface, which divides logical address space into fixed-size zones, and each zone strictly follows a sequential write constraint with a write pointer. Owing to the sequential write constraint of the ZNS, I/O requests would not be scheduled arbitrarily like the traditional SSDs with block interface. When multiple applications concurrently access one ZNS SSD hardware, the constraint deteriorates I/O blocking and causes huge unfairness. To resolve the problem, we propose a self-balance I/O scheduling dedicated for ZNS SSDs, called Fair-ZNS, to balance the slowdown among multiple applications and ensure fairness. Fair-ZNS identifies the unfair requests by the maximum slowdown value, and violently schedules these requests into the head of the queues overcoming the sequential write constraint. To eliminate the negative effect of the violent scheduling, Fair-ZNS deploys a self-balancing coordinator to fine-tune the order of the requests. Comprehensive evaluations show that Fair-ZNS alleviates I/O blocking and reduces average waiting time by 8.3×, increases fairness by 2.3×, and decreases the max slowdown by 5.1× averagely when compared to the current ZNS SSDs.

CCFTL: A novel continuity compressed page-level flash address mapping method for SSDs

Given the distinctive characteristics of flash-based solid-state drives (SSDs), such as out-of-place update scheme, as compared to traditional block storage devices, a flash translation layer (FTL) has been introduced to hide these features. In the FTL, there is an address translation module that implements the conversion from logical addresses to physical addresses. However, existing address mapping algorithms currently fail to fully exploit the mapping information generated by large I/O requests. First, based on this observation, we propose a novel continuity compressed page-level flash address mapping method (CCFTL). This method effectively compresses the mapping relationship between consecutive logical addresses and physical addresses, enabling the storage of more mapping information within the same mapping cache size. Next, we introduce two-level LRU linked list to mitigate the issue of compressed mapping entry splitting that arises from handling write requests. Finally, our experiments show that CCFTL reduced average response times by 52.67%, 16.81%, and 12.71% compared to DFTL, TPFTL, and MFTL, respectively. As the mapping cache size decreases from 2 MB to 1 MB, then further decreases to 256 KB, 128 KB, and eventually down to 64 KB, CCFTL experiences an average decline ratio of less than 3% in average response time, while the other three algorithms show an average decline ratio of 9.51%.

ML-driven risk estimation for memory failure in a data center environment with convolutional neural networks, self-supervised data labeling and distribution-based model drift determination

With the trend towards multi-socket server systems, the demand for random access memory (RAM) per server increased. The consequence are more DIMM sockets per server. Since every dual in-line memory module (DIMM), which comprises a series of dynamic random-access memory integrated circuits, has a probability of failure, RAM issues became a dominant failure pattern for servers. The concept introduced in this work contributes to improving the reliability of data centers by avoiding RAM failures and mitigating their impact. For this purpose, an ML-driven framework is provided to estimate the probability of memory failure for each RAM module. The ML framework is based on structural information between correctable (CE) and uncorrectable errors (UE). In a common memory scenario, a corrupted bit within a module can be restored by redundancy using an error correction code (ECC), resulting in a CE. However, if there is more than one corrupted bit within a group of bits covered by the ECC, the information cannot be restored, resulting in a UE.Consequently, the related task requesting the memory content, and the corresponding service may crash. There is evidence that UEs have a CE history and structural relation between the CEs. However, for the case of UEs without a CE history or of a false decision of the ML framework, we extend the total framework by engineering measures to mitigate the impact of a UE by avoiding kernel panic and using backups. The engineering measures use a mapping between physical and logical memory addresses.

A Granularity-Based Clustering Method for Reducing Write Amplification in Solid-State Drives

In recent years, solid-state drives (SSDs) that adopt NAND flash memory have been widely used as the main storage devices. In particular, NAND flash memory has a special feature of “out-of-place” updates to write the up-to-date data to a free page, and the corresponding old page will become invalid. When the number of free pages in SSDs is insufficient, garbage collection (GC) will be executed to reclaim the invalid pages in a block by erasing the block. Many studies have shown that a good hot/cold data separation (i.e., clustering) can greatly reduce the overhead of GC so as to improve the SSD performance. However, previous clustering methods usually use a static number of clusters or a fixed size of granularity (i.e., a fine-grained or a coarse-grained granularity), so they may not always perform well for different kinds of workloads. Therefore, we propose a granularity-based clustering method to adaptively adjust the size of granularity groups for an appropriate number of clusters at runtime according to the update distances of logical addresses. According to the experimental results, we can improve SSD performance by reducing the overhead of GC and decrease the write amplification. Furthermore, we can show that the proposed method can utilize a fine-grained granularity to retain the record accuracy of update distances and also utilize a coarse-grained granularity to reduce the space required to record update distances.

FlashAlloc: Dedicating Flash Blocks by Objects

For a write request, today's flash storage cannot distinguish the logical object it comes from ( e.g. , SSTables in RocksDB). In such object-oblivious flash devices, concurrent writes from different objects are simply packed in their arrival order to flash memory blocks; hence data pages from multiple objects with different lifetimes are multiplexed onto the same flash blocks. This multiplexing incurs write amplification, worsening the performance. Tackling the multiplexing problem, we propose a novel interface for flash storage, FlashAlloc. It is used to pass the logical address ranges of objects to the underlying flash device and thus to enlighten the device to stream writes by objects. The object-aware flash storage can now de-multiplex concurrent writes from multiple objects with distinct deathtimes into per-object dedicated flash blocks. In essence, the interface enables the per-object fine-grained write streaming. Given that popular data stores tend to separate writes by logical objects, we can achieve, compared to the existing solutions, transparent streaming just by calling FlashAlloc upon object creation. Also, FlashAlloc is adaptive to workload changes, and liberates the stream conflicts in the multi-tenant environment. Our experimental results using an open-source SSD prototype demonstrate that FlashAlloc can reduce the device-level write amplification factor (WAF) under RocksDB, F2FS, and MySQL by 1.5, 2.5, and 0.3, respectively and improve their throughput by 2.7x, 1.8x, and 1.2x, respectively. Also, FlashAlloc can mitigate the WAF interference among tenants: when running RocksDB and MySQL together on the same SSD, FlashAlloc reduced WAF from 2.5 to 1.6 and doubled their throughputs.

A novel scheme based on coarse‐grained localization and fine‐grained isolation for defending against Sybil attack in low power and lossy networks

AbstractDue to the lack of security mechanisms and sensor resources, the IPv6 Routing Protocol for Low power and Lossy networks (RPL) is vulnerable to various attacks, among which Sybil attack has received a lot of attention. This paper proposes a novel scheme based on coarse‐grained localization and fine‐grained isolation (CLFI) for defending Sybil attack. In CLFI, normal neighbor nodes are identified based on received signal strength indicator (RSSI). To further identify Sybil nodes, a physical address identifier called is defined, which is calculated as the difference of RSSI at two different receivers when they are receiving the same packet. In order to facilitate the calculation of , a set of anchor nodes are deployed to broadcast the received RPL control packets. Then Sybil behaviors can be detected by comparing the physical address identifier with the logical address embedded in the received packets. The proposed CLFI scheme has been completely implemented in the Contiki operating system. The extensive evaluation in comparison with the state‐of‐the‐art scheme indicates that CLFI can quickly localize and isolate Sybil nodes.

Effect of Sliding Windows Technique on the Performance of TCP/IP Networks

Abstract Two basic strategies have developed by network designers to deal including errors. by adding extra information to data before sending. such approach is to comprise sufficient extra information to make destination to infer what the sent data should be, or it possible to add only sufficient extra information to let destination to infer that errors have been occurred, however not which error then have it ask re-send defected data. Previous strategy utilizes errors correcting mechanism and latter uses errors detecting mechanism. Utilize of errors correcting mechanism is named as Forward Error Correction (FEC). In this thesis, sliding window has been implemented over Multi-Protocol Label Switching (MPLS). Therefore, MPLS send data from one node to other node on network depend on short path labels instead of logical addresses in network layer, in addition to that MPLS is connection oriented compared to IP network. Finally, we have study and analyze sliding technique performance over MPLS from delay, throughput and packet loss point of view. It is show that go back N has belter performance compared to selective repeat in term of throughput.

Influences of well contact on multiple-cell upsets in 28 nm SRAM

In order to study the effects of the feature size reduction and well contact placement on the characterization of topology patterns and the charge collection mechanism of device heavy ion single event multiple upset on a nanometer scale, the heavy ion single event effect experiment on the domestic 28 nm static random-access memory (SRAM) is carried out on the experimental platform of HI-13 heavy ion accelerator in Beijing. Based on the mapping relationship between the logical address and physical address of the device, the experimental data are processed, and the 28 nm SRAM heavy ion single event upset cross section curves, multiple upset percentage, and multiple upset topology patterns are obtained. The results are compared with those of heavy ion single event effect experiments in 65 nm SRAM, showing that under the influences of factors such as feature size reduction and lower operating voltage, the heavy ion single event upset threshold and the bit upset saturation cross section of 28 nm SRAM decrease significantly. In the direction perpendicular to the well, owing to the reduced 28 nm SRAM feature size, even if the single nucleon energy of the incident high LET (linear energy transfer) heavy ion is low, its deposited charge is sufficient to affect the three SRAM cells across the well direction due to the combined effect of ion track coverage, well potential modulation caused by the parasitic bipolar amplification effect and carrier diffusion, resulting in the fact that the 28 nm SRAM topology pattern has a shape of <i>n</i> rows × 3 columns, which poses new challenges and requirements for the anti-radiation hardened technology with scrubbing and EDAC (error detection and correction). Owing to the global well contact deployment, the charge deposited by the incident ions in the well far away from the well contact is difficult to discharge quickly, and the parasitic bipolar amplification effect lasts longer. The charge sharing competition between two p-channel metal oxide semiconductor in SRAM cell causes the single event upset recovery, which is the fundamental reason why the discontinuity of multiple upset topology pattern appears in 28 nm SRAM. This study provides a new anti-radiation hardened idea for suppressing the single event upset by using the parasitic bipolar amplification in the future.

CLUSTER ROUTER BASED ON ECCENTRICITY

In this paper, a cluster router based on eccentricity was worked out, related to the field of telecommunications, especially, to the field of message transmission. Messages in this router are transmitted as packets along the route specified in it between devices connected to the network. Each node in this network is assigned a unique address, thanks towhich routing can be accelerated. Each router forms a routing map, thanks to the calculated eccentricity of nodes, with which the physical route of the packet is selected at the logical address of the cluster. In addition, the routing map is stored in the register and non-volatile memory of the device to prevent information loss. To analyze this cluster device, a fractal analysis of the UV-flower model network was carried out and the information dimensions of Tsallis and Renyi were calculated.

Cost and Risk Prediction in Road Transportation of Hazmat by ANFIS Trained with PSO, FA, HBBO and ICA

This paper proposes adaptive neuro-fuzzy inference system (ANFIS) to predict the risk with its aggregated cost (CR) of an accident in road transportation of hazardous material, the aim is to provide a more accurate and reliable data for the safety of transportation. The determination risk index by the conventional methods such as Risk graphs and deterministic approaches may lead to imprecise values due to the uncertainties, in both parameters and models. The proposed technique is a hybrid schema, which combines the main advantageous of fuzzy logic (address uncertainties) and neural network (learn from a given data). In other hand our study seeks to tune the parameters of the proposed model by particle swarm optimization (PSO), firefly algorithm (FA), imperialist competitive algorithm (ICA) and human based-behavior optimization (HBBO) and hence optimize the performance of ANFIS. The simulation result of this work and the comparative analysis shows that ANFIS yield height performance and the ANFIS-PSO was the outstanding one in the training phase, while ANFIS-FA gives better results in the testing process.

HIPA: A hybrid load balancing method in SSDs for improved parallelism performance

NAND Flash-based SSDs have been widely adopted as underlying storage devices in storage systems thanks to high random performance in the SSDs. Because of inherent rich parallelism resources (channel, chip, plane, and die) inside an SSD, many researchers pay much attention on parallelism improvement. Page allocation policies (static and dynamic page allocation) in an SSD aim to translate logical addresses of I/O requests on the host into physical addresses in flash memory space. Existing static page allocation policies suffer from severe load unbalance inside SSDs. Dynamic allocation policies employed in high-performance SSDs address the load balancing issue. However, dynamic allocation-based I/O requests flow into fewer parallelism resources, deteriorating read I/O-requests parallelism. Recognizing that SSD performance can be optimized by reducing read parallelism loss, we propose a hybrid page allocation strategy named HIPA to fully exploit the advantages of dynamic and static allocation to achieve read/write parallelisms inside an SSD. HIPA embraces a load prediction mechanism to monitor die-level load in real-time, thereby determining a page allocation policy based on the status of die-level load. A static page allocation policy is triggered in case of balanced die-level load. When performance degrades due to imbalance in die-level load, HIPA dynamically changes the gear to a dynamic allocation policy, aiming to balance the load on dies. Thus, HIPA achieves the maximum read parallelism rather than crumbling write performance. Conducting the extensive experiments, we validate the advantages of HIPA in terms of average response time, plane-level write, and erase standard deviation. The findings unveil that compared with the four popular page allocation policies (CWDP, CHIP-D, DIE-D, and PLANE-D), HIPA slashes the average response time by up to 58% with an average of 20% and 81% with an average of 33% compared with the dynamic allocation (DIE-D) with the lowest response time and the static strategy, respectively; (2) drives up the write standard deviation degree of the static strategy by up to 44%; (3) improves erase standard deviation rate by up to 43%.

Remap-Based Inter-Partition Copy for Arrayed Solid-State Drives

The internal copy (IC) is a simple, yet powerful in-storage processing function, which changes the locations of data blocks without invoking any data transfer between the host and storage. Owing to the out-of-place update constraint of flash memory, solid-state disks (SSDs) employ a flash translation layer (FTL) to manage the logical-to-physical address translation. By leveraging the address indirection feature of SSDs, the IC can be processed only by remapping flash pages to new logical addresses without flash read/write operations. In the existing studies on remap-based IC, SSDs were assumed to have only a single FTL instance. However, recent large-capacity SSDs adopt an arrayed architecture including multiple FTL controllers, where each controller runs an FTL instance to manage its own partitioned address space. For the arrayed SSDs, inter-partition copy requests cannot be handled by address remapping because each partition is managed by a different FTL instance. In this study, we propose an inter-partition remap technique for IC-enabled arrayed SSDs. Additionally, we present the block allocation technique to minimize the number of inter-partition copy requests. Our proposed IC techniques were implemented on an actual arrayed SSD, and showed significant performance improvements compared to the previous remap techniques in several use cases.

An In-Depth Survey of Bypassing Buffer Overflow Mitigation Techniques

Buffer Overflow (BOF) has been a ubiquitous security vulnerability for more than three decades, potentially compromising any software application or system. This vulnerability occurs primarily when someone attempts to write more bytes of data (shellcode) than a buffer can handle. To date, this primitive attack has been used to attack many different software systems, resulting in numerous buffer overflows. The most common type of buffer overflow is the stack overflow vulnerability, through which an adversary can gain admin privileges remotely, which can then be used to execute shellcode. Numerous mitigation techniques have been developed and deployed to reduce the likelihood of BOF attacks, but attackers still manage to bypass these techniques. A variety of mitigation techniques have been proposed and implemented on the hardware, operating system, and compiler levels. These techniques include No-EXecute (NX) and Address Space Layout Randomization (ASLR). The NX bit prevents the execution of malicious code by making various portions of the address space of a process inoperable. The ASLR algorithm randomly assigns addresses to various parts of the logical address space of a process as it is loaded in memory for execution. Position Independent Executable (PIE) and ASLR provide more robust protection by randomly generating binary segments. Read-only relocation (RELRO) protects the Global Offset Table (GOT) from overwriting attacks. StackGuard protects the stack by placing the canary before the return address in order to prevent stack smashing attacks. Despite all the mitigation techniques in place, hackers continue to be successful in bypassing them, making buffer overflow a persistent vulnerability. The current work aims to describe the stack-based buffer overflow vulnerability and review in detail the mitigation techniques reported in the literature as well as how hackers attempt to bypass them.

Improving NVM Lifetime Using Task Stack Migration on Low-End MCU-Based Devices

Tiny embedded devices are cost and energy-sensitive, and high-density emerging non-volatile memory (NVM) can help reduce energy consumption at a fraction of the cost. However, high-density NVM has low write endurance compared to volatile memory, so it is vulnerable to write concentration. Most NVM lifetime improvement studies in the existing embedded environment have distributed writes by modifying the mapping relationship between physical and logical addresses. However, applying the existing wear leveling techniques in low-end MCUs such as ARM Cortex M3/M4 that use only physical addresses is hard. Therefore, we wear-level the write-heavy stack area to improve the NVM lifetime in low-end MCUs. However, since the stack of bare metal applications is difficult to move during runtime, we implement the migration function targeting the task stack of FreeRTOS. The task stack moves based on time, and to avoid the pointer validation problem caused by the movement of the task stack, we migrate the stack under safe conditions. In addition, FreeRTOS uses a single heap to preferentially allocate to low free space, which reduces the degree of freedom where the stack moves, reducing the effect of distributing the writes. To alleviate this problem, we add another heap for the stack migration and introduce circular dynamic allocation in the heap. Through our experiments, the proposed method was about 19.6% larger than the ideal case of maximum write, and the computational overhead was about 0.2%.

Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder

This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode.

DeepPrefetcher: A Deep Learning Framework for Data Prefetching in Flash Storage Devices

In today's information-driven world, data access latency accounts for the expensive part of processing user requests. One potential solution to access latency is prefetching, a technique to speculate and move future requests closer to the processing unit. However, the block access requests received by the storage device show poor spatial locality because most file-related locality is absorbed in the higher layers of the memory hierarchy, including the CPU cache and main memory. Besides, the utilization of multithreading results in an interleaved access request making prefetching at the storage level more picky using existing prefetching techniques. Toward this, we propose and assess DeepPrefetcher, a novel deep neural network inspired context-aware prefetching method that adapts to arbitrary memory access patterns. DeepPrefetcher learns the block access pattern contexts using distributed representation and leverage long short-term memory learning model for context-aware data prefetching. Instead of using the logical block address (LBA) value directly, we model the difference between successive access requests, which contains more patterns than LBA value for modeling. By targeting access pattern sequence in this manner, the DeepPrefetcher can learn the vital context from a long input LBA sequence and learn to predict both the previously seen and unseen access patterns. The experimental result reveals that DeepPrefetcher can increase an average prefetch accuracy, coverage, and speedup by 21.5%, 19.5%, and 17.2%, respectively, contrasted with the baseline prefetching strategies. Overall, the proposed prefetching approach surpasses other schemes in all benchmarks, and the outcomes are promising.

Pruning Deep Reinforcement Learning for Dual User Experience and Storage Lifetime Improvement on Mobile Devices

Background segment cleaning in log-structured file system has a significant impact on mobile devices. A low triggering frequency of the cleaning activity cannot reclaim enough free space for subsequent I/O, thus incurring foreground segment cleaning and impacting the user experience. In contrast, a high triggering frequency could generate excessive block migrations (BMs) and impair the storage lifetime. Prior works address this issue either by performance-biased solutions or incurring excessive memory overhead. In this article, a pruned reinforcement learning-based approach, MOBC, is proposed. Through learning the behaviors of I/O workloads and the statuses of logical address space, MOBC adaptively reduces the number of BMs and the number of triggered foreground segment cleanings. In order to integrate MOBC to resource-constraint mobile devices, a structured pruning method is proposed to reduce the time and space cost. The experimental results show that the pruned MOBC can reduce the worst case latency by 32.5%-68.6% at the 99.9th percentile, and improve the storage endurance by 24.3% over existing approaches, with significantly reduced overheads.

ITRIM: I/O-Aware TRIM for Improving User Experience on Mobile Devices

TRIM is a recommended command to deliver data invalidation information of the file system to flash storage. It is issued on both system level and device level. Since it can reduce the number of data copies during device-level garbage collection (DGC), TRIM has been widely used to improve the endurance and performance of mobile devices. Contrary to the common belief, this work identifies that the default TRIM scheme has both merit and drawback to the performance of mobile devices, especially in flash-friendly file system (F2FS), which is a commonly used file system in mobile devices. On one hand, TRIM can reduce garbage collection migration to prolong the flash lifetime as well as improving I/O throughput; On the other hand, TRIM may induce I/O contentions. This article proposes a new TRIM scheme, iTRIM, to distribute the timing overheads to system idle time. To further reduce I/O contention and improve I/O performance, the design of iTRIM considers the TRIM size, and the logical addresses' pattern of victim invalidated data. Experimental results show that iTRIM can minimize I/O contentions while retaining the benefits of the default TRIM scheme for endurance and performance.

Controllable growth and flexible optoelectronic devices of regularly-assembled Bi2S3 semiconductor nanowire bifurcated junctions and crosslinked networks

Regularly assembled structures of nanowires, such as aligned arrays, junctions and interconnected networks, have great potential for the applications in logical circuits, address decoders, photoelectronic devices and transparent electrodes. However, for now it is still lack of effective approaches for constructing nanowire bifurcated junctions and crosslinked networks with ordered orientations and high quality. Herein, we report the controlled growth of Bi2S3 semiconductor nanowire bifurcated junctions and crosslinked networks with well-aligned directions and high crystalline degree by utilizing the proportional lattice match between nanowires and substrates. Taking advantages of the “tip-to-stem splice” assembly of individual nanowires, the precise orientation alignments of Bi2S3 semiconductor nanowire bifurcated junctions and crosslinked networks were successfully realized. The controlled growth mechanism and structural evolution process have been elucidated by detailed atomic structure characterizations and modeling. The highly crystal quality and direct energy bandgap of as-assembled photodetectors based on individual bismuth sulfide nanowires enabled high photoresponsivity and fast switch time under light illumination. The three-terminal devices based on nanowire bifurcated junctions present rapid carrier transport across the junction. The flexible photodetectors based on nanowire crosslinked networks show very minimal decay of photocurrent after long-term bending test. This work may provide new insights for the guided construction and regular assembly of low-dimensional ordered functional nanostructures towards advanced nanotechnologies.