Logic Scheme Research Articles

Performance assessment of adiabatic quantum cellular automata

We investigate the feasibility of an adiabatic logic scheme for cellular automaton systems recently proposed by Tóth and Lent [J. Appl. Phys. 85, 2977 (1999)], based on structured arrays of six-dot cells and on the use of a four-phase trapezoidal clock. With respect to the original quantum cellular automaton (QCA) concept, focused on ground state computation, a clocked scheme would have the advantage of being immune to the presence of metastable states and would allow pipelined operation, at the expense of additional complexity, due to the clock distribution circuitry. Based on realistic cell geometries and material systems, we have evaluated the obtainable switching times of QCA cells, and have determined the region in the parameter space that allows operation at a reasonable clock speed.

Hierarchical Fuzzy Logic Scheme with Constraints on the Fuzzy Rule

Abstract This paper presents the hierarchical fuzzy system where the outputs of the previous layer are not used in the IF-parts, but used only in the THEN-parts of the fuzzy rules in the next layer. A certain class of functions is shown to be approximated to any degree of accuracy by the proposed hierarchical fuzzy system. The ball and beam control system is simulated to demonstrate the feasibility of the proposed scheme.

Experimental demonstration of ground state laser cooling with electromagnetically induced transparency.

Ground state laser cooling of a single trapped Ca(+)on is achieved with a technique which tailors the absorption profile for the cooling laser by exploiting electromagnetically induced transparency. Using the Zeeman structure of the S(1/2) to P(1/2) dipole transition we achieve up to 90% ground state probability. The new method is robust, easy to implement, and proves particularly useful for cooling several motional degrees of freedom simultaneously, which is of great practical importance for the implementation of quantum logic schemes with trapped ions.

All-optical free-space processing for optical communication signals

All-optical free-space architecture can find many interesting applications in optical communications in case of packet-oriented data processing. An example of an all-optical system able to perform data processing operations is described and experimented. Logic schemes characterized by high modularity and flexibility are reported. An optical implementation is proposed by using an elementary switching unit realized with CdTe:In crystal. The unit is optically controlled and operates with beams at typical communication wavelengths. Preliminary experimentation in ns regime at 1550 nm is shown.

Extension of inductor voltage control to three-phase buck-type AC-DC converter

A novel inductor voltage control (IVC) method capable of achieving near unity power factor is being proposed for buck-type AC-DC pulsewidth-modulated (PWM) converters. In this method, the input inductor voltages are kept within a hysteresis band about a sinusoidal template, thus ensuring sinusoidal input currents. This control method is much less sensitive to parameter and control variations than the existing delta modulation control (DMC) method. A companion paper has introduced the IVC method for the case of a single-phase buck-type converter. In the present paper, problems involved in direct extension of the IVC method to a three-phase buck converter are discussed first. Following this, a new switching logic scheme is proposed which enables these problems to be overcome and for IVC (as well as DMC) to be extended to a three-phase converter as well. Detailed simulation and experimental results have been provided to verify the expected good performance with IVC. The proposed IVC method has potential in applications such as those requiring AC-DC rectifiers with current limiting.

Low-power adiabatic computing with NMOS energy recovery logic

An NMOS energy recovery logic (NERL) scheme is introduced which exhibits high throughput with low energy consumption due to efficient energy transfer and recovery using adiabatic logic and bootstrapping. NERL achieves dramatic energy savings, is insensitive to output load capacitance and is less dependent on the power-clock frequency.

A SAT Solver Using Reconfigurable Hardware and Virtual Logic

In this paper, we present the architecture of a new SAT solver using reconfigurable logic and a virtual logic scheme. Our main contributions include new forms of massive fine-grain parallelism, structured design techniques based on iterative logic arrays that reduce compilation times from hours to minutes, and a decomposition technique that creates independent subproblems that may be concurrently solved by unconnected FPGAs. The decomposition technique is the basis of the virtual logic scheme, since it allows solving problems that exceed the hardware capacity. Our architecture is easily scalable. Our results show several orders of magnitude speedup compared with a state-of-the-art software implementation, and also with respect to prior SAT solvers using reconfigurable hardware.

Discrete correlation processor as a building core of a digital optical computing system: architecture and optoelectronic embodiment

In this paper we present a general-purpose discrete correlation processor (DCP) expected to be the building core block of a digital optical computing system. The DCP-1 is embodied by optoelectronic devices such as a VCSEL and a complementary metal-oxide silicon photodetector. The application targets of the DCP-1 are optical interconnection and various types of digital optical computing. It is expected that digital optical computing techniques coupled with the optoelectronic technology will provide large capability and flexibility in information processing. Introduction of a processing scheme of optical array logic enlarges the applicable field of the DCP-1 as well as its processing capability. With the experimental DCP-1 a bit error rate smaller than 10(-9) was obtained for A . B? operation under a 500-kHz clock rate.

Redundant interconnections for fault-tolerant digital optical computing

We show how multilayer optical-interconnect-based digital logic systems can be made fault-tolerant by distributed redundancy tech- niques implementable at the gate level, while incurring the expense of an increased number of gates with greater individual fan-in and fan-out. We demonstrate that braided logical interconnections between redundantly doubled, tripled, and quadrupled NOR gates enable the correction of device and interconnection errors. We present an extrapolated error analysis for the quadding, doubling, and tripling schemes, which shows the quadratic and cubic dependence of the system error on device error rates, in comparison with the linear relationship of a nonredundant sys- tem. Because the interconnections between the braided circuits are quite regular, they appear to be very amenable to optical implementations, and with the appropriate choice of device topology employing sparse device placement they are compatible with the regular, layered structure of conventional shift-invariant digital optical computer interconnects, without a penalty in circuit depth or latency. We show device topologies and interconnection architectures for the optical implementation of a fault-tolerant quadded programmable two-shuffle interconnection system that use holographic shift-invariant interconnects. Using these redundant optical logic schemes with only moderate device error probabilities, ex- tremely low system error rates can be achieved. © 1999 Society of Photo- Optical Instrumentation Engineers. (S0091-3286(99)01303-3) Subject terms: optical interconnects; optical computing.

Modelling And Control Of Engines: A Case Study

Internal combustion engines (ICEs) are challenging to model and control due to their model uncertainties and nonlinearities which pose operating problems for classical controllers. Fuzzy logic is well suited to this problem since an accurate model is not needed for design, and, in addition, due to its adaptiveness to inherent system nonlinearities and parameter variations. The objectives of this paper are two-fold: (1) to present a case-study to identify the model parameters for a portable ICE, and (2) to present a case-study to design and implement a fussy logic scheme for engine governing. The developed control scheme uses dual fuzzy logic modules. One of the modules is based on conventional fuzzy schemes and the other is a simple two membership scheme to reduce oscillations. For maximum performance, this second module requires adaptive adjustment of its gains in response to the engine's current operating condition. Laboratory test procedures and control implementation results are presented.

Accurate differential global positioning system via fuzzy logic Kalman filter sensor fusion technique

The ability to determine an accurate global position of a vehicle has many useful commercial and military applications. The differential global positioning system (DGPS) is one of the practical navigation tools used for this purpose. However, the DGPS has limitations arising from slow updates, signal interference, and limited accuracy. This paper describes how vehicle rate sensors ran be used to help a DGPS overcome these limitations. The theoretical background for the sensor fusion is based on the principle of Kalman filtering and a fuzzy logic scheme. Validity of the method was verified by using experimental data from an actual automobile navigating around an urban area. The results demonstrated that the path of the automobile can be continuously traced with high accuracy and repeatability, in spite of the limitations of the DGPS.

Rapid single-flux-quantum dual-rail logic for asynchronous circuits

Dual-rail logic circuit elements based on rapid single-flux-quantum (RSFQ) technology have been designed and simulated. The proposed circuits can operate asynchronously, since dual-rail data include timing information in themselves. Therefore dual-rail logic scheme has a possibility of solving some problems of RSFQ circuits with flow clocking, which would become more serious as operating speed and complexity of the circuit increase. Implementation of RSFQ dual-rail AND and XOR cells is described. A scheme of transfer-ring data from a flow-clocked circuit to a parallel dual-rail circuit is also proposed, which a fully asynchronous dual-rail demultiplexer.

A LOGIC SCHEME FOR REGULATING SAFE OPERATION OF RESEARCH REACTORS

This work presents a logic scheme for regulating the safe operation of research reactors in accordance with the IAEA Safety Series SS-35-S2 and revised by the Codes of Fedral Regulations 10 CFR. It emphasizes the regulatory inspection and enforcement (RI&E) program in the reactor operation licensing phases. It is developed to provide information ,guidance and recommendations to be taken when constructing a RI&E program to be applied in the operational phase of the Egyptian research reactors. The RI&E procedures for regulating safe operation of research reactors are presented as flow charts, and then developed as a computer logic scheme. The software program is efficient , friendly, simple and interactive in nature such that the program asks the user certain questions about essential steps that guide the RI&E for research reactors and the user responds by (yes) or (no) and the program proceeds based on this response until all the necessary RI&E steps are accomplished. Samples of results of the RI&E software execution showing some violation cases with their inspective and corrective paths throughout the program are presented and discussed.

Testability aspects of folded source-coupled logic

Several low noise logic schemes for mixed mode integrated circuit design have been presented over the last few years. These logic approaches are used to diminish the level of switching noise generated by the digital part of the circuit. In the paper the testability of one of these approaches is analysed: folded source-coupled logic (FSCL). A basic FSCL inverter with two kind of realistic fault (bridge and open circuit, including floating gates) is simulated. The effects of the realistic faults in various observable magnitudes are presented and discussed, and some test approaches are suggested.

Top-down pass-transistor logic design

The pass-transistor based cell library and synthesis tool are constructed, for the first time, to clarify the potential of top-down pass-transistor logic. The entire scheme is called LEAP (Lean Integration with Pass-Transistors). The feature of a pass-transistor based cell is its multiplexer function and the open-drain structure. This cell has the flexibility of transistor level circuit design and compatibility with conventional cell based design. An extremely simple cell library with only seven cells combined with a synthesis tool called "circuit inventor" is compared with the conventional CMOS library that has over 60 cells combined with the state-of-the-art logic synthesis. The results show that the area, delay, and power dissipation are improved by LEAP and that the value-cost ratio is improved by a factor of three. This demonstrates that LEAP has the potential to achieve a quantum leap in value of LSI's while reducing the cost. Key issues which have to be cleared before pass transistor logic is used as the generic logic scheme replacing CMOS are also discussed.

SOI-DRAM circuit technologies for low power high speed multigiga scale memories

This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty.

Proportional-integral controllers with fuzzy tuning

Some simple fuzzy logic schemes for online tuning of proportional-integral controller parameters to improve system robustness are outlined. Simulation results indicate that, with fuzzy tuning, the reference response is well damped with adequately fast dynamics, and the maximum deviation of the disturbance response is reduced even in the case of changing plant parameters.

The first level muon trigger in the central toroid of the ATLAS experiment

We present the design of the first level muon trigger in the central toroid of the ATLAS experiment at the Large Hadron Collider (LHC). A trigger is foreseen based on fast, finely segmented gaseous detectors, Resistive Plate Chambers (RPC), to unambiguously identify the interaction bunch crossing. We describe the detectors and the logic scheme of the trigger.

Optimized Sequencing and Scheduling Algorithms for Arrival Air Traffics Based on FCFS Principles

The air traffic flow management techniques that perform scheduling for arrival traffics in terminal airspace are discussed based on FCFS principle. Four scheduling schemes, FCFS, FCFS + TA, FCFS + CPS, and FCFS+TA+CPS, are first discussed. A new kind of performance index is developed for the scheduling process optimization, which could represent a more general system performance than the average delay-time previously used. And a fuzzy logic scheme is proposed to implement the optimized scheduling algorithms.

Multilevel programmable logic array schemes for microprogrammed automata

Programmable logic arrays (PLAs) provide an efficient tool for implementation of logic schemes of microprogrammed automata (MPA). The number of PLAs in the MPA logic scheme can be minimized by increasing the number of levels. In this paper, we analyze the structures of multilevel schemes of Mealy automata, propose a number of new structures, consider the corresponding correctness conditions, and examine some problems that must be solved in order to satisfy these conditions.