Logic Replication Research Articles

Why Make Atlas Dance? Colonial Utopia that Persists in Contemporary Robotics

This paper addresses the colonialist values at the foundation of Boston Dynamics’ humanoid robot Atlas and contemporary robotics, generally, through an analysis of its dance video ‘Do You Love Me?’. This paper focuses on the concepts of ‘extractivism’ and ‘recognition’ to reveal how colonialist logic guides the human-robot relationship. I argue that Atlas is a new, posthuman colonial subject that has emerged in contemporary society and that, despite not having a sense of self and thus dodging ethical criticisms, robots such as Atlas display the succession and replication of colonial logic and practices. In other words, the desire for a colonial utopia—where we humans construct and rule the world based on the oppression and extraction of less-than-human others—haunts the robot that dances for your love. This paper thus problematizes the prevalence of colonialism in robotics and calls for reflection on the development of today’s robotics deeper than the symptoms of racism, sexism, and capitalism. Furthermore, I demonstrate how extraction as a dispossessing, dehumanizing force, and recognition as framing of false identity are two major mechanisms of colonialism that work closely together. Through the two tactics, colonialism not only serves capitalism but also deceptively obscures its existence.

Intelligent orchestration of database resources in power system

With the continuous development of cloud computing technology, the size of database clusters is getting larger and larger. The database resources in existing power systems need to be manually deployed, which puts great pressure on operation and maintenance personnel. Therefore, resource orchestration and automatic deployment are proposed and realized. This method implements a visual orchestration interface through the GoJS framework, establishes a deployment template, uses Spring template to encapsulate task execution scripts, orchestrates database instances, high-availability standby machines, and logical replication at one time, simplifying the deployment process. Practice shows that this method can be effective Reduce deployment time and improve work efficiency.

Em um mundo para gente grande, o que podem os corpos pequenos?

O texto parte de uma pesquisa de mestrado apresentada ao Programa de Pós Graduação em Psicologia Institucional, da Universidade Federal do Espírito Santo, apresentada no ano de 2019 e que se propôs a trabalhar, junto às crianças, as relações e negociações feitas com as normas de gênero e sexualidade. As crianças apareceram em situações e lugares diversos, com destaque para duas pracinhas de bairro, onde se deu a maior parte da pesquisa. A dissertação não tinha como objetivo fazer uso de teorias desenvolvimentistas, descrever e enquadrar as crianças em categorias, pois entendeu-se que isso também seria a reprodução das lógicas adultocêntricas. Movimentos crianceiros foram considerados em sua potência de existir por si e, por essa autonomia, foi possível visualizar como eles conseguem fazer questão sobre os lugares e identidades que os adultos insistem em reafirmar sobre os corpos através da diferença sexual. Os resultados da pesquisa apontaram que as crianças conseguem agir taticamente dentro das questões de gênero, subvertendo a lógica das estratégias que incidem sobre seus corpos e os colocam constantemente na posição de projetos de adultos. A partir da pesquisa, pensamos como as crianças podem indicar, nos diversos campos de experiência humana, outros modos de se relacionar e estar no mundo

Clustering without replication in combinatorial circuits

The modern integrated circuit is one of the most complex products engineered to date. It continues to grow in complexity as years progress. As a result, very large-scale integrated (VLSI) circuit design now involves massive design teams employing state-of-the-art computer-aided design (CAD) tools. One of the oldest, yet most important CAD problems for VLSI circuits is physical design automation, where one needs to compute the best physical layout of millions to billions of circuit components on a tiny silicon surface (Lim in Practical problems in VLSI physical design automation, Springer, Dordrecht, 2008). The process of mapping an electronic design to a chip involves several physical design stages, one of which is clustering. Even for combinatorial circuits, there exists several models for the clustering problem. In particular, we consider the problem of clustering in combinatorial circuits for delay minimization, without permitting logic replication (CN). The problem of clustering for delay minimization when logic replication is allowed (CA) has been well-studied and is known to be solvable in polynomial time (Lawler et al. in IEEE Trans Comput 18(1):47–57, 1969; Rajaraman and Wong, in: 30th ACM/IEEE design automation conference, pp 309–314, 1993). However, unbounded logic replication can be quite expensive. It follows that CN is an important problem. We show that selected variants of CN are NP-hard. We also obtain approximability and inapproximability results for some of these problems. A preliminary version of this paper appears in Donovan et al. (in: 9th International conference on combinatorial optimization and applications, COCOA 2015, Proceedings, pp 334–347, 2015).

High-Throughput and Area-Efficient FPGA Implementations of Data Encryption Standard (DES)

One of the most popular standards for protecting confidential information is the Data Encryption Standard (DES). Although it has been replaced by the Advanced Encryption Standard (AES), it is still widely used in Automatic Teller Machines (ATM’s), smartcards, and mobile phone SIM cards. In this paper, we present area-efficient and high-throughput FPGA implementations of the DES which are developed using the Xilinx FPGA ISE design suite. In fact, we propose modifications on the fastest DES design reported in the literature and achieve 1.1 times higher speed. Also, we introduce an 8-stage pipelined design that needs only 0.75 times the registers and consumes 0.65 times the power of a similar 16-stages pipelined design. High-speed design and synthesis optimization techniques including pipelining, register retiming, and logic replication are used. Post- layout synthesis results show that the proposed implementations achieve high throughput-to-area ratio. To make a fair comparison, the proposed designs were synthesized using matching FPGA devices as being used by other implementations reported in the literature.

Towards zero-overhead static and adaptive indexing in Hadoop

Hadoop MapReduce has evolved to an important industry standard for massive parallel data processing and has become widely adopted for a variety of use-cases. Recent works have shown that indexes can improve the performance of selective MapReduce jobs dramatically. However, one major weakness of existing approaches is high index creation costs. We present HAIL (Hadoop Aggressive Indexing Library), a novel indexing approach for HDFS and Hadoop MapReduce. HAIL creates different clustered indexes over terabytes of data with minimal, often invisible costs, and it dramatically improves runtimes of several classes of MapReduce jobs. HAIL features two different indexing pipelines, static indexing and adaptive indexing. HAIL static indexing efficiently indexes datasets while uploading them to HDFS. Thereby, HAIL leverages the default replication of Hadoop and enhances it with logical replication. This allows HAIL to create multiple clustered indexes for a dataset, e.g., one for each physical replica. Still, in terms of upload time, HAIL matches or even improves over the performance of standard HDFS. Additionally, HAIL adaptive indexing allows for automatic, incremental indexing at job runtime with minimal runtime overhead. For example, HAIL adaptive indexing can completely index a dataset as byproduct of only four MapReduce jobs while incurring an overhead as low as 11 % for the very first of those job only. In our experiments, we show that HAIL improves job runtimes by up to 68 $$\times $$ × over Hadoop. This article is an extended version of the VLDB 2012 paper (Dittrich et al. in PVLDB 5(11):1591---1602, 2012).

Timing-driven logic restructuring for nano-hybrid circuits

As the feature size of the integrated circuits (ICs) scales down, the future of nano-hybrid circuit looks bright in extending Moore's Law. However, mapping a circuit to a nano-fabric structure is vexing due to connectivity constraints. A mainstream methodology is that a circuit is transformed into a nano-fabric preferred structure by buffer insertion to high fan-out gates. However, it may result in timing degradation. Logic replication is a traditional way to split high fan-out gates in logic synthesis but may not be suitable for high fan-out gates with high fan-ins. In this article, a timing-driven logic restructuring framework at the gate level is proposed. The proposed framework identifies the high fan-out gates from a given gate netlist according to the fan-out threshold, following by the restructuring of high fan-out gates through the application of logic replication and buffer insertion. To improve circuit timing from a global perspective, latent critical edges are identified to avoid entrapping critical paths during the restructuring. Experimental results on ISCAS benchmarks indicate that 8.51% timing improvement and 6.13% CPU time reduction can be obtained traded with 4.16% area increase on an average.

FuSnap: Fuzzy Control of Logical Volume Snapshot Replication for Disk Arrays

This paper presents FuSnap, a fuzzy-logic-based controller that monitors and controls the snapshot process of a logical storage volume in a disk array. As disks do not linearly respond to the arrival rate of user accesses, FuSnap makes use of fuzzy logic as the means to achieve better control of their response time. The goal of the FuSnap controller is to reduce the response time caused by the copy-on-writes (CoWs) that occur during the snapping of a storage logical volume. The FuSnap controller, based on the response time of user accesses, makes the decision on whether to proceed with a CoW or a redirect-on-write when a source logical volume is being copied to a snapshot logical volume. The benefits of FuSnap approach are twofold. First, significant reductions in response time of user requests are obtained with the FuSnap approach over the traditional CoW snap approach. Second, these reductions in response time make the point-in-time copy of data a process less disruptive for database users. FuSnap was verified with two setups using Hewlett-Packard UniX workstations, one setup with eight and the other with 32 disks.

Autonomous temperature control technique in VLSI circuits through logic replication

A temperature reduction technique at the gate level that reduces the peak temperature through thermal-aware logic replication is presented. The technique identifies the hottest part of a given gate-netlist, extracts this from the netlist and replicates it in order to migrate the computation from one unit to the copied one whenever it exceeds a given maximum threshold temperature. The resulting gate netlist is then replaced using a thermal-aware floorplanner in order to maximise temperature reduction gain. To allow the migration from one unit to the other without any timing penalty, multiplexors and de-multiplexors between both units are inserted as well as a simple control unit with a thermal sensor on each replicated unit. Our technique ensures that only those parts of the circuit that have a high power density are replicated, and provides an autonomous hardware thermal-controlling mechanism that self-regulates itself and allows the context to swap to any replicated unit without any timing penalty. An entire temperature reduction framework is built on the top of this technique that incorporates a thermal simulator, thermal-aware floorplanner, power estimators as well as a graphical interface to manage these tools. Experimental results show that the proposed technique efficiently identifies the hottest parts of a gate netlist, replicates these and inserts the de-muxes and muxes, lowering the final peak temperature by up to 20.27°C. Further, it reduces the overall leakage power by up to 35.98%.

An Approach to Placement-Coupled Logic Replication

This paper presents a set of techniques for placement-coupled timing-driven logic replication. Two components are at the core of the approach. First, is an algorithm for optimal timing-driven fanin tree embedding; the algorithm is very general in that it can easily incorporate complex objective functions (e.g., placement costs) and can perform embedding on any graph-based target. Second, the replication tree is introduced, which allows to induce large fanin trees from a given circuit, which can then be optimized by the embedder. The authors have built an optimization engine around these two ideas and report promising results for the field-programmable gate array (FPGA) domain including clock period reductions of up to 36% compared with a timing-driven placement from versatile place and route (VPR) (Marquardt , 2000) and almost double the average improvement of local replication (Beraudo and Lillis, 2003). These results are achieved with modest area and runtime overhead. In addition, issues that arise due to reconvergence in the circuit specification are addressed. The authors build on the replication tree idea and enhance the timing-driven fanin tree embedding algorithm to optimize subcritical paths, yielding even better delay improvements.

SPaRre: selective partial replication for concurrent fault-detection in FSMs

We discuss SPaRe: selective partial replication, a methodology for concurrent fault detection in finite state machine (FSMs). The proposed method is similar to duplication, wherein a replica of the circuit acts as a predictor that immediately detects errors by comparison to the original FSM. However, instead of duplicating the FSM, SPaRe selects a few prediction functions which only partially replicate it. Selection is guided by the objective of minimizing the incurred hardware overhead without compromising the ability to detect all faults, yet possibly introducing fault-detection latency. SPaRe is nonintrusive and does not interfere with the encoding and implementation of the original FSM. Experimental results indicate that SPaRe achieves significant hardware overhead reduction over both duplication and test vector logic replication (TVLR), a previously reported concurrent fault-detection method. Moreover, as compared to TVLR, SPaRe also reduces the average fault-detection latency for detecting all permanent faults.

Temporal logic replication for dynamically reconfigurable fpga partitioning

In this paper, we propose the idea of temporal logic replication in dynamically reconfigurable field-programmable gate array partitioning to reduce the communication cost. We show that this is a very effective means to reduce the communication cost by taking advantage of the slack logic capacity available. Given a K-stage temporal partition, the min-area min-cut replication problem is defined and we present an optimal algorithm to solve it. We also present a flow-based replication heuristic which is applicable when there is a tight area bound that limits the amount of possible replication. In addition, we show a correct network flow model for partitioning sequential circuits temporally and propose a new hierarchical flow-based performance-driven partitioner for computing initial partitions without replication.

Min-cut partitioning with functional replication for technology-mapped circuits using minimum area overhead

Logic replication is known to be an effective technique to reduce the number of cut nets in partitioned circuits. A new replication model called functional replication is particularly useful for partitioning technology-mapped circuits. Functional replication differs from traditional replication because it considers the functional dependency of the different output signals of a logic cell on its input signals. Functional replication can lead to a higher reduction in the number of cut nets than traditional replication. In this paper, we give the first theoretical treatment of the min-cut partitioning problem with functional replication. We present a novel two-phase algorithm to compute a min-cut bipartition of a technology-mapped circuit with functional replication using a minimum amount of area overhead. Additionally, we show that our algorithm can be applied to improve the solution produced by any area-constrained functional replication partitioning heuristic.

Evaluation and optimization of replication algorithms for logic bipartitioning

Logic partitioning is an important area of very large scale integration computer aided design and there have been numerous approaches proposed. Logic replication, the duplication of logic in order to minimize communication between partitions, can be an effective component of a complete partitioning solution. In this paper we seek a better understanding of the important issues in logic replication. By adding new optimizations to existing algorithms we are able to significantly improve the quality of these techniques, achieving up to 13.9% better results than the best existing replication techniques. When integrated into our already state-of-the-art (nonreplication) partitioner, we improve overall cutsizes by 38.8%, while requiring the duplication of at most 7% of the logic.

Partial scan with preselected scan signals

This paper deals with partial scan approaches that select scan signals oblivious to the availability of flip-flops (FFs). Such approaches can greatly reduce the number of scan signals since maximum freedom is presented when selecting signals. However, to actually scan the selected signals, one must make them drive FFs. We study the problem of replicating and retiming a circuit to make a set of scan signals drive FFs while preserving the set of cycles broken by the signals. We present a framework for solving the problem. Based on the framework, we present an efficient algorithm which also minimizes the amount of logic replication.

Network-flow-based multiway partitioning with area and pin constraints

Network flow is an excellent approach to finding min-cuts because of the celebrated max-flow min-cut theorem. For a long time, however, it was perceived as computationally expensive and deemed impractical for circuit partitioning. Recently, the algorithm FBB successfully applied network flow to two-way balanced partitioning. It for the first time demonstrated that network flow was a viable approach to circuit partitioning. In this paper, we present FBB-MW, which is an extension of FBB, to solve the problem of multiway partitioning with area and pin constraints. Experimental results show that FBB-MW outperforms previous approaches for multiple field programmable gate array partitioning. In particular, although FBB-MW does not employ logic replication and logic resynthesis, it still outperforms some other algorithms, which allow replication and resynthesis for optimization.

Minimum replication min-cut partitioning

Logic replication has been shown to be very effective in reducing the number of cut nets in partitioned circuits. Liu et al. (see IEEE Trans. Computer-Aided Design, vol. 14, p. 623-30, May 1995) considered the circuit partitioning problem with logic replication for separating two given nodes and presented an algorithm to determine a partitioning of the minimum possible cut size. In general, there are many possible partitioning solutions with the minimum cut size and the difference in the required amount of replication by these solutions can be significant. Since there is a size constraint on each component of the partitioning in practice, it is desirable to also minimize the amount of replication. In this paper, we present a network-flow based algorithm to determine an optimum replication min-cut partitioning that requires minimum replication. We show that the algorithm can be generalized to separate two given subsets of nodes giving an optimum partitioning of the minimum possible cut size using the least possible amount of replication. We also show that our algorithm can be used to improve the solutions produced by any existing size-constrained replication min-cut partitioning algorithm by reducing the cut size and shrinking the replication set.

Min-cut replication in partitioned networks

Logic replication has been shown empirically to reduce pin count and partition size in partitioned networks. This paper presents the first theoretical treatment of the min-cut replication problem, which is to determine replicated logic that minimizes cut size. A polynomial time algorithm for determining min-cut replication sets for k-partitioned graphs is derived by reducing replication to the problem of finding a maximum flow. The algorithm is extended to hypergraphs and replication heuristics are proposed for the NP-hard problem with size constraints on partition components. These heuristics, which reduce the worst-case running time by a factor of O(k/sup 2/) over previous methods, are applied to designs that have been partitioned into multiple FPGA's. Experimental results demonstrate that min-cut replication provides substantial reductions in the numbers of FPGA's and pins required.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The Role of the Simulator in Drilling Operations

Summary This paper presents a reference on the simulation industry—the state of the art, how the simulator is used, different types of simulators, and how simulator use applies to the drilling industry. For those contemplating buying or developing a simulator, this paper cites the uses and pitfalls of the simulator in drilling applications. This paper is intended to aid the engineer and manager in making decisions pertaining to the development, acquisition, or use of a drilling simulator.