Quantum-dot Cellular Automata Logic Research Articles

A systematic and bibliometric review of the latest techniques in quantum-dot computers

When designing and manufacturing logic circuits, minimal energy loss, high packing densities, and functioning at Tera-hertz frequencies are highly sought characteristics. Due to the rapid growth of large-scale integration technology, producing a dependable architecture with minimal power consumption is crucial. Quantum dot Cellular Automata (QCA) is a potential substitute to the traditional semiconductor-based technique for constructing logic circuits in the nano-scale range due to the promising implementation of these highly desired properties. QCA cells may be used to create arbitrary circuits by following a few straightforward layout criteria. In contrast to conventional computers, quantum computers work faster by utilizing the principles of quantum physics. It is crucial to consider what applications these devices may aid, given that quantum computing technologies are on the cusp of commercialization and quantum dominance. As a result, this paper offers a thorough and bibliometric assessment of the most recent quantum-dot computing methods. In order to present some intriguing directions for any future study, it provides the benefits and drawbacks of the evaluated mechanisms and their significant problems. According to the results, reversible logic in QCA may be regarded as one of the most hopeful technologies for next-generation computers.

A general and efficient clocking scheme for majority logic in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is a nanotechnology with characteristics of high speed, high density, and low power consumption to be one of the strong alternatives to replace traditional CMOS in the future in theory. Its primitive is a majority gate, instead of AND/OR logic in CMOS, which can reduce the complexity of a system and thus its overhead. In this paper, a general and efficient clocking scheme to facilitate the design of circuits using majority gates in QCA is proposed as their scale extends. Each clock zone in this scheme is an octagon adjacent to the other three zones. This results in four input and two output directions in clock zones 0 and 2 to design circuits with majority gates, two input and four output directions in clock zones 1 and 3 to improve the flexibility of circuit routing. Besides, this scheme utilizes the flexible feedback paths for sequential circuits, equivalent clock zones, and elastic QCA wires for efficiently wiring circuits. This paper then takes a one-bit full adder and an SR-latch as examples to show the generality and efficiency of the proposed clocking scheme in designing combinational and sequential circuits, respectively. An arithmetic unit is also taken as an example to illustrate its high expansibility in designing larger circuits. Experimental results show that the proposed clocking scheme is more suitable for QCA circuit design in contrast to previous clocking schemes.

A deep analysis of the image and video processing techniques using nanoscale quantum-dots cellular automata

The advancement of small electrical components into the nanoscale range opens up opportunities for massively parallel computing systems. Quantum-dot Cellular Automata (QCA) is a potential novel nanoelectronics technique that fits image processing requirements well. QCA circuits are typically highly stable, quick, and utilize little energy. Because studies about QCA logic image processing are starting up, the suggested contribution will initiate a new line of inquiry in the real-time video and image processing domain. Noise reduction, face identification, feature extraction, segmentation, skeletonizing, thickening, thinning, object detection, form extraction, and tracking are all examples of image processing. This article describes how to use QCA technology for image processing in various ways. The fundamentals of image processing approaches and the function of QCA in them are covered. The findings demonstrate that a more effective layout based on QCA technology would reduce power consumption and computational complexity in the long run. We anticipate that this compendium will give readers an overview of the advances made in quantum image processing and pique their curiosity in doing a more complex investigation in the field.

Towards the realization of regular clocking-based QCA circuits using genetic algorithm

Quantum-dot cellular automata (QCA) has gained an exclusive research focus on the current CMOS due to low power dissipation, less circuit area occupancy, and computational speed. The effectiveness of a QCA circuit is affected by the primary logic (majority vote and inverter). Hence, the minimization of these primitives for QCA logic circuit synthesis becomes an extreme necessity. The genetic algorithm (GA) has a more important effect on the synthesis of cost-effective circuits. Besides, the underlying regular clocking scheme is significant in systematic cell layout, scalability, and reliability. This paper emphasizes the design of a cost-effective circuit, applying a genetic algorithm incorporating the regular clock. Multi-output functions are taken into account here to minimize with the help of a genetic algorithm. All the circuits are synthesized by utilizing RES, USE clocking scheme. The analytical study indicates the significance of the genetic algorithm on the design of QCA using the regular clock.

An efficient structure for designing a nano-scale fault-tolerant 2:1 multiplexer based on quantum-dot cellular automata

Quantum-dot Cellular Automata (QCA) is a unique and appealing technique for developing and implementing high-performance and low-power digital circuits at the nanometer scale. In this technology, fault-tolerant circuits guarantee reliability circuits through cells redundancy. Therefore, fault-tolerant and optimized architecture are very important in designing a wide range of QCA circuits. However, although there are some QCA structures for multiplexer designs in the literature, QCA characteristics can be used to design a more optimized multiplexer rather than blindly modeling traditional logic in QCA. As a result, we developed an alternate version of the proposed approaches that leverage fault-tolerant design methodologies. In this article, a new structure for a fault-tolerant 2:1 multiplexer in QCA technology is suggested. Cell redundancy on the wire, NOT gates and majority gates are used. Simulating the suggested designs and demonstrating their correctness was done with QCADesigner 2.0.3. When the additional cell or single missing cell fault occurs in the QCA architecture, the suggested fault-tolerant multiplexer can achieve 90% fault tolerance.

Optimized area efficient quantum dot cellular automata based reversible code converter circuits: design and energy performance estimation

Quantum-dot cellular automata (QCA) based circuit designs are creating a surge in transistorless computational technologies. Due to its quasi-adiabatic switching resulting in extremely low leakage power dissipation as there is no continuous path. These circuits also enjoy extremely high packaging density of the order of 10 $$^{12}$$ devices/ $$\hbox {cm}^2$$ because of its extremely scaled area of 18 nm x 18 nm along with very high 100 GHz frequency of operation. Further the loss of bit information could be abolished by reversible logic computing. This thereby realizes an energy efficient logic operations owing to bijective relation between inputs and outputs in reversible logic. This work investigates the code converter circuits which converts 4-bit binary code to excess-3 code and vice versa based on reversible QCA logic gates for the first time. Moreover an area efficient design for 4-bit binary to gray and vice-versa code converters also designed here. All these four code converter circuits are designed using reversible logic gate Feynman and Peres gates by deploying the QCA Designer and Designer-E tool v2.0.3. Finally the in depth performance estimation of the proposed circuits in terms of circuit complexity, quantum cost and energy dissipation are also presented here. Moreover, these QCA based circuits provide a strong evidence that reversible logic based QCA circuits can be efficiently deployed for these code converter circuits.

Synthesis of composite logic gate in QCA embedding underlying regular clocking

Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative technologies for current CMOS technology. It has the advantage of computing at a faster speed, consuming lower power, and work at Nano- Scale. Besides these advantages, QCA logic is limited to its primitive gates, majority voter and inverter only, results in limitation of cost-efficient logic circuit realization. Numerous designs have been proposed to realize various intricate logic gates in QCA at the penalty of non-uniform clocking and improper layout. This paper proposes a Composite Gate (CG) in QCA, which realizes all the essential digital logic gates such as AND, NAND, Inverter, OR, NOR, and exclusive gates like XOR and XNOR. Reportedly, the proposed design is the first of its kind to generate all basic logic in a single unit. The most striking feature of this work is the augmentation of the underlying clocking circuit with the logic block, making it a more realistic circuit. The Reliable, Efficient, and Scalable (RES) underlying regular clocking scheme is utilized to enhance the proposed design?s scalability and efficiency. The relevance of the proposed design is best cited with coplanar implementation of 2-input symmetric functions, achieving 33% gain in gate count and without any garbage output. The evaluation and analysis of dissipated energy for both the design have been carried out. The end product is verified using the QCADesigner2.0.3 simulator, and QCAPro is employed for the study of power dissipation.

Efficient majority logic subtractor design using multilayer crossover in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is a potential upcoming nanotechnology for designing digital circuits with high performance. A subtractor is an important arithmetic circuit used in many digital circuits. An efficient multilayer full subtractor design is proposed using majority logic in QCA. The proposed design has only 53 cells and occupies a small area of about 0.03 μm2. Using the proposed subtractor, a 4-bit ripple borrow subtractor with 256 cells and an area of about 0.20 μm2 is realized. Verification and simulation are done using QCADesigner. Defect analysis is also done for the proposed subtractor. Energy dissipation of the proposed designs is done using QCADesignerE tool.

Design of fault tolerant majority voter for error resilient TMR targeting micro to nano scale logic

The shrinking size of transistors for satisfying the increasing demand for higher density and low power has made the VLSI circuits more vulnerable to faults. Therefore, new circuits in advanced VLSI technology have forced designers to use fault tolerant techniques in safety-critical applications. Also, the presence of some faults (not permanent) due to the complexity of the nanocircuit or its interaction with software results in malfunctioning of circuits. The fault tolerant scheme, where majority voter plays the core role in triple modular redundancy (TMR), is being implemented increasingly in digital systems. This work targets to implement a different fault tolerant scheme of majority voter for the implementation of TMR using quantum-dot cellular automata (QCA), viable alternative nanotechnology to CMOS VLSI. The fault masking ability of various voter designs has been analysed in details. The fault masking ratio of the proposed voter (FMV) is 66% considering single/multiple faults. Simulation results establish the validation of proposed logic in QCA which targets nano-scale devices. The proposed logic is also suitable for conventional CMOS technology, which is verified with the Cadence tool.

Design of fault tolerant majority voter for error resilient TMR targeting micro to nano scale logic

The shrinking size of transistors for satisfying the increasing demand for higher density and low power has made the VLSI circuits more vulnerable to faults. Therefore, new circuits in advanced VLSI technology have forced designers to use fault tolerant techniques in safety-critical applications. Also, the presence of some faults (not permanent) due to the complexity of the nanocircuit or its interaction with software results in malfunctioning of circuits. The fault tolerant scheme, where majority voter plays the core role in triple modular redundancy (TMR), is being implemented increasingly in digital systems. This work targets to implement a different fault tolerant scheme of majority voter for the implementation of TMR using quantum-dot cellular automata (QCA), viable alternative nanotechnology to CMOS VLSI. The fault masking ability of various voter designs has been analysed in details. The fault masking ratio of the proposed voter (FMV) is 66% considering single/multiple faults. Simulation results establish the validation of proposed logic in QCA which targets nano-scale devices. The proposed logic is also suitable for conventional CMOS technology, which is verified with the Cadence tool.

Area-Delay-Energy aware SRAM memory cell and M × N parallel read/write memory array design for quantum dot cellular automata

Quantum dot Cellular Automata (QCA) is an emerging nanotechnology, potentially suitable to replace the popular technologies like Complementary Metal Oxide Semiconductor (CMOS) technology. The evolution of QCA has become prominent due to high operating frequency, nanoscale device and zero current low power nanotechnology. However, the Area-Delay-Energy aware QCA logic circuit design remains a prime concern in this post CMOS technology. In this work the primary attention is given to build efficient QCA circuits. The motivation of this work is to propose Efficient VLSI design in terms of Area, Delay, Power and PDP (Power delay product). Different methodologies are reported to design a combinational and sequential circuit in QCA technology. An extensive focus is given in designing of 3 different QCA based Area-Delay-Energy aware SRAM memory cells, parallel read/write M × N SRAM memory array and peripherals like decoder and multiplexer. Since appropriate signal distribution network (SDN) is an essential aspect to deign QCA circuit, it has also been reported a delay aware signal distribution methodology applicable for any type of QCA logic circuit design. The significant results of this research finding are expressed in terms of Area-Delay-Energy dissipation tradeoff. When compared with respective to the state of art, the performance metric of proposed QCA based memory cells are excelled, on an average 40% reduction in area, 33% and 22% drop in delay and energy dissipation respectively are achieved for proposed three different memory cell design.

Test Pattern Generator for MV-Based QCA Combinational Circuit Targeting MMC Fault Models

Quantum-dot-Cellular Automata (QCA) is emerging as one of the alternatives for Integrated Circuit Technology considering the scaling limitations of current Complementary Metal Oxide Semiconductor (CMOS) technology. Being at molecular scale, defects are more likely to occur in QCA devices. Therefore, the substantial development of QCA-oriented defects, its corresponding fault models and test generation is required. This paper addresses the fault model caused by multiple missing cells defect and test generation for these faults for QCA circuits. We have shown that the single missing cell considerations are not enough. Correspondingly, in this paper, testing properties for the detection of fault caused by multiple missing cell defects in QCA devices mainly Majority Voter (MV) are proposed. Even though there are many advanced ATPGs available for CMOS technology, to demonstrate very special MV-based properties with reference to the test pattern generation process and to open the path for advanced combinational and sequential ATPGs specific to MV-based QCA circuits, the extension of basic Automatic Test Pattern Generator is proposed here. The proposed test generation algorithm is guided by the extended Sandia Controllability Observability Analysis Program (SCOAP) testability measures especially for QCA logic primitives.

An Efficient Inverter Logic in Quantum-Dot Cellular Automata for Emerging Nanocircuits

Quantum-dot cellular automata (QCA) has been advocated as one of the most propitious nanoelectronic technologies. The fault rates in QCA are very high due to its susceptibility to cell deposition defects. Also, the power requirements of QCA are getting more critical to avoid either over-design for power rails or unreliability under high-performance stress. Among the different primitive logic structure of QCA, the inverter is keyed out to enable more reliable as well as low-power design. This work proposes a novel approach to generate stimulus for low-power dissipation in QCA logic primitives (inverter) in order to obtain worst-case power scenarios. Hybridizing rotated and non-rotated QCA cell together with a new low-power inverter tile structure in QCA is proposed. Further, the functional characterization of the proposed inverter tile is investigated. Kink energy estimation, as well as simulation results, is considered for verifying the circuit layout and functionality. Moreover, a composable logic block is synthesized that realizes triple fanout (with two inverted output). The reliability of these logic primitives is also extended by implementing full adder and XOR circuit.

Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis

Quantum dot cellular automata (QCA) is a hopeful technology in the field of nanotechnology that seems to suite well with signal-processing needs. It is concerned with great interest because of its benefits such as ultra-low power consumption, small size and can operate at one Terahertz. The multiply accumulator (MAC) unit is considered as one of the essential operations in digital signal processing (DSP). In the real-time DSP systems, several applications like speech processing, video coding, and digital filtering etc. require MAC operations. However, the power dissipation and area are the most significant aspects in these systems. Here, the authors design low power MAC unit based on QCA technology. QCADesigner version 2.0.3 is used to validate the accuracy of the proposed circuit. The reliability of this unit is taken at different temperatures. The power dissipation is estimated using QCAPro tool. The total power consumed by this unit is 2.183 μW. The proposed circuit has 90% improvement in terms of power over complementary metal–oxide–semiconductor (CMOS) circuits. Since the works in the field of QCA logic signal processing has started to progress, the suggested contribution will give rise to a new thread of research in the field of real-time signal and image treatment.

Design and implementation of finite state machine using quantum-dot cellular automata

Moore's law states that the number of transistors per square inch on integrated circuits has doubled approximately every two years; this is true for CMOS based VLSI circuit design. Quantum-dot cellular automata (QCA) replaces CMOS based VLSI technology. The assembly of quantum dots replaces transistors which is said to be 'quantum-dot cellular automata', an emerging nanotechnology in the field of quantum electronics. Such type of circuit can be used in many digital applications and has an advantage of reduced area utilisation. Quantum mechanics and cellular automata are together said to be QCA. QCA technology has advantages like small size and high speed. CMOS technology uses transistors to create a logic gates but in QCA technology, logic gates and wires are created by using QCA cells. The basic logic gates like AND, OR, inverter, majority gates are implemented. Many combinational and sequential circuits are designed by using these basic gates. This paper aims at the design of finite state machines and its use in vending machine and traffic light controller were discussed. The circuit was designed and the functionality of those was verified using QCADesigner tool.

Design and analysis of efficient QCA reversible adders

Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS technology. In a QCA structure, information destruction plays an essential role in the overall heat dissipation, and in turn in the power consumption of the system. Therefore, reversible logic, which significantly controls the information flow of the system, is deemed suitable to achieve ultra-low-power structures. In order to benefit from the opportunities QCA and reversible logic provide, in this paper, we first review and implement prior reversible full-adder art in QCA. We then propose a novel reversible design based on three- and five-input majority gates, and a robust one-layer crossover scheme. The new full-adder significantly advances previous designs in terms of the optimization metrics, namely cell count, area, and delay. The proposed efficient full-adder is then used to design reversible ripple-carry adders (RCAs) with different sizes (i.e., 4, 8, and 16 bits). It is demonstrated that the new RCAs lead to 33% less garbage outputs, which can be essential in terms of lowering power consumption. This along with the achieved improvements in area, complexity, and delay introduces an ultra-efficient reversible QCA adder that can be beneficial in developing future computer arithmetic circuits and architectures.

Implementation of Full Adder Using 5-Input Majority Gate

In this paper full adder was created employing five-input majority gate according to Quantum-Dot Cellular Automata (QCA) innovation. We used the QCA logic in our modified structure to reduce the delay. That report details the structure furthermore investigate associated with QCA dependent 1-bit full adder design for minimal energy purposes. This method permits decreasing energy expenditure, delay, additionally location involving electronic circuits.

Robust and efficient QCA cell-based nanostructures of elementary reversible logic gates

Increasing device density and reducing energy consumption are challenging issues in integrated nanoscale circuits. Reversible logic in quantum-dot cellular automata (QCA) nanotechnology is emerging as a promising candidate to overcome these issues and to introduce new computation paradigms with unique features like nanoscale feature size and ultra-low power dissipation. For the first time, QCA cell-based designs of reversible Feynman, Toffoli, Fredkin, and Peres gates are presented in this paper. These elementary gates are usually used in the synthesis of reversible circuits. The proposed layouts utilize electrostatic interactions between cells within QCA configurations to perform desired functions. All the robust designs are evaluated in terms of hardware complexity and power dissipation using QCADesigner and QCAPro simulation tools. The efficient QCA layouts of proposed gates have notable improvements as compared to the existing ones in terms of gate delay, cell count, area occupation, quantum cost, leakage energy, and switching energy. As a result, the proposed elementary gates via QCA cell level-based design are good candidates for building and developing high-level nanoelectronic reversible circuits.

Efficient design of BinDCT in quantum‐dot cellular automata (QCA) technology

Here, the authors present a hardware design of fast multiplierless forward binary discrete cosine transform (BinDCT) based on quantum-dot cellular automata (QCA) technology. This new technology offers several features such as: small size, ultralow power consumption, and can operate at 1 THz. The simulation results in QCA Designer software confirm that the proposed circuit works well and can be used as a high-performance design in QCA technology. The analysis obtained from the implementation of QCA BinDCT indicates that the proposed architecture is superior to the existing based on classic metal-oxide (complementary metal-oxide semiconductor technology) technology. Here, the authors are going to introduce highly BinDCT module scaled with ultra-low power consuming. The proposed circuit requires 50% fewer power consuming compared to previous existing designs. The proposed architecture can attain a throughput of 800 mega pixel per second (Mpps). To design and verify the proposed architecture, QCADesigner tool and QCAPro tool are, respectively, employed for synthesis and power consumption estimation. Since the works in the field of QCA logic image processing have only started to bloom, the proposed contribution will engender a new thread of research in the field of real-time image and video treatment.

The role of the tunneling matrix element and nuclear reorganization in the design of quantum-dot cellular automata molecules

Mixed-valence molecules provide an implementation for a high-speed, energy-efficient paradigm for classical computing known as quantum-dot cellular automata (QCA). The primitive device in QCA is a cell, a structure with multiple quantum dots and a few mobile charges. A single mixed-valence molecule can function as a cell, with redox centers providing quantum dots. The charge configuration of a molecule encodes binary information, and device switching occurs via intramolecular electron transfer between dots. Arrays of molecular cells adsorbed onto a substrate form QCA logic. Individual cells in the array are coupled locally via the electrostatic electric field. This device networking enables general-purpose computing. Here, a quantum model of a two-dot molecule is built in which the two-state electronic system is coupled to the dominant nuclear vibrational mode via a reorganization energy. This model is used to explore the effects of the electronic inter-dot tunneling (coupling) matrix element and the reorganization energy on device switching. A semi-classical reduction of the model also is made to investigate the competition between field-driven device switching and the electron-vibrational self-trapping. A strong electron-vibrational coupling (high reorganization energy) gives rise to self-trapping, which inhibits the molecule's ability to switch. Nonetheless, there remains an expansive area in the tunneling-reorganization phase space where molecules can support adequate tunneling. Thus, the relationship between the tunneling matrix element and the reorganization energy affords significant leeway in the design of molecules viable for QCA applications.