Logic Circuit Diagrams Research Articles

Encrypt ECG signals based on the optimized 4-bit absolute value comparator

As people become more conscious of private information security and advancements in Electrocardiogram (ECG) identity identification technology, the need to encrypt private data intensifies. New wearable medical devices continuously gather vast amounts of personal health data, underscoring the urgency of safeguarding privacy. This paper focuses on encrypting and decrypting rich characteristic signals like ECG. It delves into the core aspects, including the logic circuit diagram of a four-bit digit absolute comparator using Complementary Metal Oxide Semiconductor (CMOS) technology and optimizing delay through logic effort to reduce power consumption. XOR gates and other gate circuits, as well as complement subtraction principles, are employed in building logic gates. Calculating delay involves selecting the longest critical path and determining the specific parameters (g, h, and p) for each logic gate. Subsequently, energy consumption is computed using a formula, revealing a trade-off between energy and delay. After optimization, the circuit's energy consumption is 184.832, and the delay is 34.13. In summary, the 4-bit absolute value detector plays a crucial role in encryption, addressing the growing concern for privacy and data security.

高周波IH応用単相ダイレクトAC-ACコンバータの固定周波数電力制御手法

The direct ac-ac converter is an effective circuit topology for high-efficient power conversion in induction heating (IH) applications. The conventional pulse frequency modulation (PFM)-based power control scheme causes audible noises between the adjacent IH loads which operate at different switching frequencies. As a solution for the technical issue, a new fixed-frequency power control methodology for a single-phase direct ac-ac converter is proposed in this paper, featuring a wide range of soft switching operation and robustness for abnormal load conditions. The principle of the proposed pulse modulation is explained in detail with the logic circuit diagram of controller. The performances of the ac-ac converter and power controller are demonstrated by simulation, after which the effectiveness is revealed in terms of the power control range and soft switching operation.

BiCAM-based automated scoring system for digital logic circuit diagrams

Abstract In online education, it is critical for the quality of education to evaluate and grade the assignments or examinations that students upload to the system. However, it is time-consuming to determine how well the circuit drawings prepared for the digital logic course, which is a fundamental course in computer engineering and similar disciplines, are not only correct but also compatible with the truth table. Content-addressable memory (CAM), also known as associative memory, is a data storage and retrieval unit. Typically, it is used instead of the conventional memories in fast-paced and time-sensitive applications such as address lookup in Internet routers, databases, and pattern recognition. CAMs implement the search process by comparing the content itself with a key instead of finding the address like the conventional memories. To see the effect of using binary content-addressable memory-based memory on the time spent scoring hand or digital-drawn logic circuits, it is compared with various data structures commonly used in logic simulation programs. I found a significant relationship (O(1)), indicating that the proposed architecture reduces the time complexity in the search process. This expression is the same as time complexity in hash tables.

Development of a Boolean logic simulator based on Quine McClusky algorithm

This paper presents the development of an educational simulation tool for solving Boolean logic equations using Quine McCluskey’s algorithm. Unity3D development environment was used to provide an interface for the design of the software front end. A custom built version of Javascript was used to write the back end code that drives the algorithm. Based on the output parameters decided on by the user for either sum of product (SOP) or product of sum (POS) approaches, the software provides an interactive user interface displaying: (i) the truth table with a maximum of six inputs (ii) the Karnaugh Map as well as the generated corresponding simplified logic equation and (iii) the generated logic circuit diagram. The results of the simplified Boolean expressions and logic circuits generated by the developed tool were compared with manually calculated solutions and available html and console based implementations and were found to be accurate. Keywords : Boolean Logic Simulator, Logic Circuit, Quine McClusky Algorithm, Karnaugh Map, Digital Electronics.

SKETRACK: Stroke-Based Recognition of Online Hand-Drawn Sketches of Arrow-Connected Diagrams and Digital Logic Circuit Diagrams

Digitalization of handwritten documents has created a greater need for accurate online recognition of hand-drawn sketches. However, the online recognition of hand-drawn diagrams is an enduring challenge in human-computer interaction due to the complexity in extracting and recognizing the visual objects reliably from a continuous stroke stream. This paper focuses on the design and development of a new, efficient stroke-based online hand-drawn sketch recognition scheme named SKETRACK for hand-drawn arrow diagrams and digital logic circuit diagrams. The fundamental parts of this model are text separation, symbol segmentation, feature extraction, classification, and structural analysis. The proposed scheme utilizes the concepts of normalization and segmentation to isolate the text from the sketches. Then, the features are extracted to model different structural variations of the strokes that are categorized into the arrows/lines and the symbols for effective processing. The strokes are clustered using the spectral clustering algorithm based on p-distance and Euclidean distance to compute the similarity between the features and minimize the feature dimensionality by grouping similar features. Then, the symbol recognition is performed using modified support vector machine (MSVM) classifier in which a hybrid kernel function with a lion optimized tuning parameter of SVM is utilized. Structural analysis is performed with lion-based task optimization for recognizing the symbol candidates to form the final diagram representations. This proposed recognition model is suitable for simpler structures such as flowcharts, finite automata, and the logic circuit diagrams. Through the experiments, the performance of the proposed SKETRACK scheme is evaluated on three domains of databases and the results are compared with the state-of-the-art methods to validate its superior efficiency.

Hand-drawn Digital Logic Circuit Component Recognition using SVM

Hand-drawn circuit diagrams are widely used in engineering fields, especially for the early design phases because sketch is a convenient tool to understand rough ideas of system development. Using such hand-drawn diagrams designers can focus more on the critical issues rather than on the intricate details. Electronic system design is one of the application areas in this context. To speed up the development process of such systems, hand-drawn circuits design need be transformed into the computers. The problem is that although it seems very easy for humans to recognize sketches, it is really a great challenge for the computers. This paper proposed a method to recognize components in hand drawn digital logic circuit diagram. This system used region based segmentation method to segment circuit sketch, and classified each component using Support Vector Machine that uses Fourier descriptor as the feature vector. An average of 83% circuit recognition accuracy is achieved.

Delay and Performance Estimation for a 4-bit Even Parity Bit Generator Using the Logical Effort Model

Recent digital applications require high speed and high performance designs. The circuit design can be implemented using different types of logic gates. The logic gates are classified into two types; primitive and compound (complex) gates. Any complex logic circuit diagram can be converted into primitive using one type of universal gates; such as the NAND gates or the NOR gates only. The combinational circuits and any functional block can also be implemented using the NAND or the NOR gates only. This article shows how to build a 4-bit even parity bit generator using both universal gate types: the implementation using NAND gates only and the implementation for the 4-bit even parity bit generator using NOR gates only. A performance comparison between these two implementations, with different output loads in each case, is achieved to study the impact of the output load on the circuit delay. It will also determine which type of universal gates can be used to get better performance (delay) readings by using the logical effort technique. The logical effort is a technique used to estimate the static logic circuit delay and the power dissipated by a circuit. It helps designers make their right decisions about the delay and the power for a given design before the real implementation begins.

An Android Application for Simplifying Boolean Functions

Students who are enrolled in computer-related courses need to have a fundamental knowledge and application of Boolean expressions. Learning Boolean algebra and digital logic are somehow difficult for students to grasp especially because these disciplines highly require them of critical thinking and logical understanding. To address this need, the researchers designed and developed a mobile application for Android-enabled phones that will assist the teacher in explaining the concepts of Boolean expressions to students. Developmental-experimental designs of research were used. The data gathered from the respondents were analyzed and utilized in the application development where it accepts Boolean expressions and displays the generated simplified expression, truth table, Karnaugh map, and logic circuit diagrams. The application does not require a network connection and runs only on the Android operating system. The researchers used the following tools in the development of the mobile application: Eclipse as editor, Android Software Development Kit (SDK) as a development tool, and SQLite as its database. The mobile application was tested, evaluated, and used by the respondents. Respondents agreed that the application is better than the manual procedures in simplifying Boolean expressions. Thus, this Android-based application is highly recommended as a tool for teaching Boolean expressions. Keywords- Information Technology, Boolean algebra, descriptive-developmental method, Philippines

Logic gates using high Rydberg states.

Connected logic gates can be operated on the levels of one molecule by making use of the special properties of high Rydberg states. Explicit experimental results for the NO molecule are provided as an example. A number of other options, including that of several gates concatenated so as to operate as a full adder, are discussed. Specific properties of high Rydberg states that are used are: their autoionization is delayed so that they can be distinguished from direct multiphoton ionization, during their long life such states also can decay by energy transfer to the molecular core in a way that can be controlled by the judicious application of very weak external electrical fields, and the Rydberg states can be detected by the application of an ionizing electrical field. The combination of two (or three) color photons with and without external weak fields allows the construction of quite elaborate logic circuit diagrams and shows that taking advantage of the different intramolecular dynamics of levels that differ by their excitation enables the compounding of logic operations on one molecular frame.

A similarity retrieval method of drawings based on graph representation

AbstractAn efficient method to retrieve necessary information from drawings for plant diagrams, logic circuit diagrams, etc. stored in a database is presented. In the image information retrieval systems currently in use, a keyword is assigned to each diagram and information is retrieved by the user by giving the keyword. When the features of the desired image are not registered as a keyword, however, its retrieval becomes difficult. In this paper a method is proposed in which the user shows features of the desired diagram using a sample diagram and a section similar to the sample diagram is retrieved. In this research, diagrams consisting mainly of symbols and connecting lines are considered. This kind of diagram is represented by a graph and similarities in topological features between the sample graph and graph representations of the diagrams in the database are evaluated. The retrieval is then performed based on the value obtained. The results of an experiment conducted using plant diagrams show that similar diagrams can be retrieved using this method.

An automatic circuit diagram reader with loop-structure-based symbol recognition

A high-performance logic circuit diagram reader was developed for VLSI-CAD data input. Almost all logic circuit symbols include one or more loop structures. A description is given of an efficient method for recognition of these loop-structured symbols. The proposed method consists of two processes: symbol segmentation and symbol identification. Symbol identification is achieved by a powerful hybrid method which uses heuristics to mediate between template matching and feature extraction. The entire symbol recognition process is carried out under a decision-tree control strategy. The entire recognition system for circuit diagrams is briefly explained, including character string recognition and connecting line analysis. >

A visibility—oriented construction system for logic diagrams

AbstractThe automation of each stage in the design and manufacture of computer systems is now being considered. The design language simulators, physical design systems and test systems are already in practical use. At present, however, the required verification of each stage is mostly performed manually. In consideration of this, the authors designed and developed an automatic system for constructing logic circuit diagrams (RADICS) aiming at easy manual verification and documentation. Seven criteria are specified for the visibility, which include the signal flow from input to output as well as the criteria adopted in the previous placement and routine system. This paper describes the aims and outlines of each algorithm in RADICS. The algorithms are then analyzed and evaluated.

A primary algorithm for the understanding of logic circuit diagrams

This paper describes a primary algorithm that inputs information of logic circuit diagrams by designers into a computer automatically executing a local area processing. The algorithm tracks signal lines that have thickness using a line sensor. A line sensor detects particular areas such as branches, crosses, L type junctions, logic symbol areas and so on. When the pending signal line is recognized as ending at the output-side of a logic symbol, its input-side is examined precisely and the kind (OR, AND or INVERTER), the numbers of input signal lines and so forth are recognized.