Locally Parallel Globally Sequential Research Articles

Efficient Partitioning of Algorithms for Long Convolutions and their Mapping onto Architectures

We present an efficient approach for the partitioning of algorithms implementing long convolutions. The dependence graph (DG) of a convolution algorithm is locally sequential globally parallel (LSGP) partitioned into smaller, less complex convolution algorithms. The LSGP partitioned DG is mapped onto a signal flow graph (SFG), in which each processor element (PE) performs a small convolution algorithm. The key is then to reduce the complexity of the SFG in two steps: 1. local reduction of complexity: the short Fast Fourier Transform (FFT) is used to perform the small convolution within the PE; and 2. global reduction of complexity: the short FFTs within the PEs are relocated to the global level, where redundant short FFT operations are eliminated. The remaining operation within the PEs is now a simple element-wise multiply-add. After a graph transform, the structure of the SFG kernel is recognized as a set of parallel small convolutions. If we use the short FFT to perform these short convolutions, we come to our final realization of the long convolution algorithm. The computational complexity of this realization is close to the optimum for convolutions, that is, O(N log N). Our approach is thus achieving this N log N ---low without having to implement large-size FFTs. We use, instead, small FFT blocks. The advantage is that small FFT transforms are commercially available, and that they can even be implemented in single-chip VLSI architectures. Our final SFG is three dimensional and can be mapped efficiently onto prototype architectures or dedicated VLSI processors. We demonstrate the procedure in the paper by a design example: the implementation of a prototype convolution architecture that we designed for a real-time radar imaging system.

A Unifying Lattice-Based Approach for the Partitioning of Systolic Arrays via LPGS and LSGP

Various methods for the synthesis of systolic arrays from signal and image processing algorithms have been developed in the past few years. In this paper, we propose a technique for the partitioning problem, the problem to synthesize systolic arrays whose size does not match the problem size. Our technique generalizes most of the known lattice-based approaches to the partitioning problem and combines the multiprojection method for the synthesis of systolic arrays with the locally sequential-globally parallel (LSGP) and locally parallel-globally sequential (LPGS) partitioning schemes. Starting from (1) a k-dimensional large-size systolic array obtained from a system of n-dimensional uniform recurrences by a space-time transformation and (2) an arbitrary lattice in k-space inducing a partitioning of the array into subarrays, a small-size systolic array with a scalar-valued system clock is constructed via the LSGP or LPGS paradigm. In particular, the allocation function for the small-size array can be written in closed form and the timing function is obtained from timing functions for the subdomains, the set of operations performed by the subarrays, by simple greedy algorithms. In this way, the problem of finding optimal timing functions can in various cases be reduced to finding optimal timing functions for the subdomains. For problems of large size, these greedy algorithms seem to be preferable when compared with existing integer or non-convex programming formulations for finding (sub-)optimal timing functions. We also provide some new results, a necessary and sufficient condition for the existence of counter data flow, a formal relationship between partitionings of processor space and index space of the uniform recurrences in terms of counter data flow, and the structural equivalence between the lattice-based LSGP and LPGS schemes applied to the partitioning of index and processor space.

A Linear Systolic Array for Real-Time Morphological Image Processing

Mathematical morphology has proven to be a very useful tool for applications such as smoothing, image skeletonization, pattern recognition, machine vision, etc. In this paper we present a 1-dimensional systolic architecture for the basic gray-scale morphology operations: dilation and erosion. Most other morphological operations like opening and closing, are also supported by the architecture since these operations are combinations of the basic ones. The advantages of our design stem from the fact that it has pipeline period α = 1 (i.e., 100% processor utilization), it requires simple communications, and it is exploiting the simplicity of the morphological operations to make it possible to implement them in a linear target machine although the starting algorithm is a generalized 2-D convolution. We also propose a Locally Parallel Globally Sequential (LPGS) partitioning strategy for the best mapping of the algorithm onto the architecture. We conclude that for this particular problem LPGS is better than LSGP in a practical sense (pinout, memory requirement, etc.). Furthermore, we propose a chip design for the basic component of the array that will allow real-time video processing for 8- and 16-bit gray-level frames of size 512 × 512, using only 32 processors in parallel. The design is easily scalable so it can be custom-taylored to fit the requirement of each particular application.

An integral matrix-based technique for systematic systolic design

In this paper we consider a systematic mapping procedure for systolic arrays. Integral matrix theory provides the basic concepts used here to define projection and scheduling vectors. Unimodular matrices are defined which describe projection, timing, and bases for the processor space and a correct timing function. The use of these matrices couples the definition of correct projection and scheduling functions and provides relatively simple tools for the design. The same mathematical description furnishes a rigorous definition of the partitioning block structure, as well as the cluster set. Both partitioning schemes of locally parallel, globally sequential (LPGS) and locally sequential, globally parallel (LSGP), as well as a number of intermediate partitioning schemes, can be generated by using this technique. Folding (intended as spatial relocation of portions of processing elements) as well as a number of design constraints can also be included, and are briefly considered here. The possible application of a systolic design for low power requirements is also discussed.

A methodology for fast scheduling of partitioned systolic algorithms

Various methods for mapping signal processing algorithms into systolic arrays have been developed in the past few years. In this paper, efficient scheduling techniques are developed for the partitioning problem, i.e. problems with size that do not match the array size. In particular, scheduling for the Locally Parallel-Globally Sequential (LPGS) technique and the Locally Sequential-Globally Parallel (LSGP) technique are developed. The scheduling procedure developed exploits the fact that after LPGS and LSGP partitioning, the locality constraints are less stringent allowing for more flexibility in the choice of algorithms and inter-processor communication. A flexible scheduling order is developed that is useful in evaluating the trade-off between execution time and size of storage buffers. The benefits of the scheduling techniques are illustrated with the help of matrix multiplication and least squares examples.

On partitioning and fault tolerance issues for neural array processors

In this article, we have studied time-efficient schedule and fault-tolerant design of partitioned array processors for neural networks. First, we have applied the locally-sequential-globally-parallel (LSGP) partitioning scheme to decompose large-size neural network algorithms so that they can be mapped into array processors of smaller size. Then we have derived an optimal latency schedule, i.e., for the same decomposition the schedule outperforms any other schedule, in terms of overall execution time. We have further proposed an algorithm-based fault tolerance (ABFT) method to guarantee higher reliability for the array processor implementation.

Systematic serialisation of array-based architectures

This paper describes the use of Ruby, a language of functions and relations, to develop serialised implementations of array-based architectures. Our Ruby expressions contain parameters which can be varied to produce a wide range of designs with different space-time trade-offs. Such expressions can be obtained by applying correctness-preserving transformations to an initial simple description. This approach provides a unified treatment of serialisation schemes similar to LPGS (Locally Parallel Globally Sequential) and LSGP (Locally Sequential Globally Parallel) partitioning methods, and will be illustrated by the development of a variety of circuits for convolution.