Local Oscillator Buffer Research Articles

A Millimeter-Wave Mixer-First Receiver With LO Waveform Shaping Using Varactors

A mixer-first receiver is proposed, which uses an overlap-suppressed local oscillator (LO) signal for the mixer switching. A sinusoidal LO wave can be shaped into a sharper waveform by adding a second-harmonic component to the fundamental one. This is readily achieved by integrating accumulation MOS varactors with LO buffers. The receiver is implemented in a 28-nm bulk CMOS and achieves an input 1-dB gain compression power in the range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 12.6 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 14.3 dBm and a noise figure (NF) in the range of 8.4–9.6 dB at frequencies of 24–29 GHz while consuming 12.6-mW power.

A 90‐ to 115‐GHz superheterodyne receiver front‐end for W‐band imaging system in 28‐nm complementary metal‐oxide‐semiconductor

SummaryIn this paper, a broadband superheterodyne receiver (RX) front‐end for millimeter‐wave (mm‐Wave) imaging radar is presented. Realized in 28‐nm CMOS technology, the proposed RX incorporates a wideband low‐noise amplifier (LNA), double‐balanced passive mixers for the dual down‐conversion, a differential power divider, a differential intermediate frequency filters, a current‐mode‐logic divider‐by‐2, and a local oscillator buffers. Wideband technique and layout optimization are taken into consideration in the RX. A four‐stage LNA is devised to realize the high gain and low noise figure (NF) with a common‐gate input stage and three pseudodifferential common‐source stages. Optimized transistor layout and capacitor neutralization technique are developed to improve gain and noise performance. Transformer‐based matching networks with the peak‐staggered technique are adopted in the LNA to achieve a flatter gain response with a wider bandwidth (BW). The passive double‐balanced mixers are implemented with a highly symmetrical layout for broadband down‐conversion. Simulation results show that the mm‐Wave RX front‐end exhibits a BW ranging from 90 to 115 GHz. The simulated NF of our RX is 4.7 dB at 86 GHz. With a supply voltage of 1 V, the presented RX consumes 88.2‐mW power and occupies a chip size of 1.6 × 0.5 mm2 including all the testing pads. The proposed RX is suitable for W‐band imaging systems.

28-GHz CMOS Up-Conversion Mixer With Improved LO Second-Harmonic Leakage Signal Suppression for 5G Applications

A CMOS up-conversion mixer with an intermediate frequency (IF) amplifier and local oscillator (LO) buffer is presented for mobile 28-GHz-band 5G dual-conversion transceivers. A balun transformer with improved common-mode rejection ratio characteristics is proposed to improve the LO second-harmonic signal suppression, which is a problem in the up-conversion mixer of the 5G dual-conversion architecture. By applying the proposed balun transformer instead of the conventional one, a common-mode rejection ratio greater than 10 dB can be achieved at the frequencies of the LO second-harmonic leakage signal. An up-conversion mixer with an IF amplifier and LO buffer incorporating the proposed balun transformer was implemented in a 65-nm CMOS process, and it draws a current of 31.4 mA from a 1-V supply voltage. It provides a gain larger than 22.2 dB, a noise figure less than 4.1 dB, a thirdorder output intercept point higher than 4.6 dBm, and an LO second-harmonic leakage signal lower than -55.5 dBm in frequencies ranging from 26.5 GHz to 29.5 GHz. It also exhibits a suppression improvement of the LO second-harmonic leakage signal of approximately 14 dB with respect to an up-conversion mixer with IF amplifier and LO buffer using the conventional balun transformer. The proposed up-mixer with IF amplifier and LO buffer is the first one reported that addresses the 2LO leakage issue and the first demonstration of 2LO leakage signal suppression improvement for a 5G mmWave dual-conversion single-quadrature transmitter.

2.4-GHz Low-Power Low-IF Receiver With a Quadrature Local Oscillator Buffer for Bluetooth Low Energy Applications

In this brief, a 2.4-GHz low-power single-quadrature low-IF Bluetooth low energy receiver employing a quadrature local oscillator (LO) buffer is presented for Internet of Things applications. The quadrature LO buffer, which consists of common-source amplifiers with capacitive degeneration, compensating resistors, compensating PMOS transistors and LC tanks, performs quadrature generation and supplies quadrature signals to a single-quadrature mixer, thus eliminating an additional circuitry for quadrature generation in the LO path and saving dc current consumption. The implemented receiver consists of a low-noise amplifier, a G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -stage, double-balanced current-mode passive mixers, transimpedance amplifiers, an active- RC complex bandpass filter, and the quadrature LO buffer. Fabricated in a 65-nm CMOS process, the implemented receiver achieves a noise figure of 8.16 dB, a conversion gain of 54.5 dB, an image rejection ratio of 32.1 dB, and an input-referred third-order intercept point of -27.5 dBm. It draws a bias current of 2.5 mA from a nominal supply voltage of 0.8 V, and the active die area is 1.65 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A K/Ka/V Triband Single-Signal-Path Receiver With Variable-Gain Low-Noise Amplifier and Constant-Gain Phase Shifter in 28-nm CMOS

This article presents a single-signal-path tri (K/Ka/V)-band receiver (RX) featuring area/cost-effective support for various millimeter-wave phased-array applications. A triple-coupling transformer (TCT) at the common-gate input stage of the RX low-noise amplifier (LNA) is proposed for triband impedance matching and g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosting. By augmenting each low-parasitic pMOS switched inductor load with a pMOS variable resistor in parallel, the variable-gain functionality is merged into this LNA to cover a wide input-signal range in a low-overhead manner. An active single-balanced mixer (SBM) for radio frequency (RF)-intermediate frequency (IF) downconversion is adopted to eliminate a wideband balun. Poor RF-IF and local-oscillator (LO)-IF isolations and low IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> normally inherited in an SBM are avoided by setting the IF particularly. The wideband response of an on-chip LO buffer is realized through input resistor coupling and output inductor peaking. Furthermore, a constant-gain phase shifter (CGPS) at IF is proposed to benefit the orthogonal gain-and-phase control preferred by beam steering. This CGPS uses an amplitude-only feedback loop to retain the gain without baseband equalization. Fabricated in a 28-nm bulk CMOS technology, this RX exhibits variable power gains of 12.5-33.2 dB (at 24 GHz), 13.4-34.6 dB (at 33 GHz), and 3.1-32 dB (at 50 GHz) with respective minimum noise figures of 4.78, 5.12, and 6.15 dB. The respective RX 3-dB bandwidths are 20-27, 30-34.6, and 42-55.5 GHz. The measured CGPS gain variation at IF (2-4 GHz) is within 0.94 dB. This RX consumes 131 mW and occupies 1.22 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with pads in a silicon area.

Comparison of active dual‐gate and passive mixers for terahertz applications

The authors propose four versions of a dual-gate active down-conversion mixer for H-band applications. The mixer operates at a local oscillator (LO) frequency of 240 GHz. It is designed for maximum conversion gain and a large bandwidth of at least 50 GHz from 220 to 270 GHz. Furthermore, the mixer is .optimised to operate at low LO power levels beneath 0 dBm. This renders power hungry LO buffer stages redundant. Hereby, the necessary chip size and the overall power consumption of fully integrated receivers can be drastically reduced. Four different versions of the downconverter were designed. Firstly, the layout of the transistors was changed from a conventional multi-transistor cell design to a mixer topology within the multi-finger transistor cell. Secondly, two on-chip solutions to decouple the drain voltage from the intermediate frequency (IF) signal were realised to facilitate zero-IF conversion: a resistive and an active load. The results are presented and the advantages and disadvantages of the four versions for the usage in terahertz applications are thoroughly analysed. Finally, the active dual-gate mixers are compared to a state-of-the-art resistive mixer for H-band with regard to conversion gain, bandwidth, linearity, noise figure and chip size.

A Compact 281–319 GHz Low-Power Downconverter MMIC for Superheterodyne Communication Receivers

This article presents a fully integrated first downconversion stage for a superheterodyne receiver for high data rate communication at 300 GHz. It comprises a frequency multiplier-by-three, an active dual-gate downconverter, and an LNA. The chip was fabricated in a 35-nm InGaAs-based metamorphic high-electron-mobility transistor technology. The downconverter was designed to be used for different local oscillator (LO) frequencies between 70 and 80 GHz and intermediate frequency (IF) frequencies from 65 to 95 GHz, to create multiple channels for real-time full-duplex communication in the terahertz region. It achieves a conversion gain of 14 dB without IF amplification and 3-dB bandwidth of 25 GHz in the desired upper sideband from 288 to 313 GHz and an estimated NF of 6.6 dB. Without the LNA, the conversion gain of the circuit is $-$ 10 dB and it shows 3-dB bandwidth of 38 GHz in a frequency range from 281 to 319 GHz. Finally, the millimeter-wave monolithic integrated circuit (MMIC) will be compared in detail to a similar state-of-the-art downconverter using a resistive mixer and a necessary additional LO buffer stage in the same technology targeting the identical application. While exhibiting a better conversion gain and bandwidth and occupying only 40% of chip area, the presented downconverter consumes 70% less dc power than the MMIC with a resistive mixer.

A 2.4-GHz Quadrature Local Oscillator Buffer Insensitive to Frequency-Dependent Loads for Bluetooth Low Energy Applications

In this letter, a 2.4-GHz quadrature local oscillator (LO) buffer insensitive to frequency-dependent loads is presented for Bluetooth low energy (BLE) applications. An LC tank is used as a load in the proposed buffer to provide a sufficient voltage gain and large voltage swing at the operating frequencies of BLE. Furthermore, the effect of the frequency-dependent impedance of the LC tank on the gain and phase mismatches is reduced by adding compensating transistors. The proposed buffer can provide accurate quadrature signals without additional circuitry in the LO path, minimizing the current consumption of the receiver. It is implemented in 65-nm CMOS technology. It achieved a voltage gain of 5.6 dB, a gain mismatch less than 0.3 dB, a phase mismatch less than 1.1°, and an output ${P} _{{1dB}}$ of 3 dBm. It draws an average current of 3.8 mA from a supply voltage of 0.8 V. The active die area is 0.55 mm2.

A Low-Power 70–100-GHz Mixer-First RX Leveraging Frequency-Translational Feedback

Massive multiple-input multiple-output (MIMO) wireless communication systems mandate strict power and area requirements for receiver (RX) front ends, while noise performance can be relaxed due to averaging over the array. To address these needs at mm-waves, we propose an integrated mixer-first RX, leveraging frequency-translational feedback and passive voltage gain, to minimize the RX power consumption. An analytical model is developed, thus providing useful intuition on optimal design choices. A 28-nm CMOS prototype achieves S11<; -10 dB, NF <; 10 dB, and ~20-dB conversion gain over all the mm-wave E -band (71-95 GHz), while consuming only 12 mW including the local oscillator buffers. The power can be further reduced to 8 mW, with similar performance over a 74-94-GHz RF bandwidth.

A high‐linearity Ka‐band CMOS down‐conversion mixer

AbstractThis article presents a high‐linearity Ka‐band complementary metal–oxide–semiconductor (CMOS) down‐conversion mixer. The mixer comprises an RF transconductance stage, switching stage, local oscillator buffer, and intermediate frequency (IF) buffer, and employs modified multiple gate transistors for high linearity. The intermodulation and gain characteristics are analyzed, revealing that the proposed IF buffer can enhance the linearity performance without a gain reduction. Implemented in 65‐nm CMOS technology, the proposed mixer consumes 23 mW and occupies a core chip area of 0.54 mm2. The mixer achieves a conversion gain of 9.3 to 11.1 dB, a noise figure of 8.4 to 9.2 dB, and an output third‐order intercept point of 15.6 to 23.6 dBm at an RF frequency of 37 to 41 GHz.

A 28-GHz CMOS Down-conversion Mixer with Low-magnetic-coupled Source Degeneration Inductors for 5G Applications

This paper presents a 28-GHz CMOS millimeter-wave down-conversion mixer employing a derivative superposition linearization technique with our proposed low-coupling source degeneration inductors for 5G cellular communication systems to improve the linearity performance of the downconversion mixer. The proposed low-magneticcoupled source degeneration inductors avoid the linearity degradation gap between the schematic design without considering magnetic coupling and the post-layout design with considering magnetic coupling effect due to the source degeneration inductors. The down-conversion mixer with local oscillator buffer is implemented using a 65-nm CMOS technology, and it draws a 21 mA from a 1-V supply voltage. It achieves a gain of 10.1 dB, noise figure below 10 dB, and third-order output intercept point of 19.3 dBm from 26.5 to 29.5 GHz.

A Low-Power Low-Noise Decade-Bandwidth Switched Transconductor Mixer With AC-Coupled LO Buffers

In this paper, a modified switched transconductor mixer structure is proposed to realize a low-power, low-noise, and wideband mixer, in which, a transconductor stage with fixed dc operating point is switched by the ac-coupled local oscillator (LO) signal. In this way, only a small LO signal is required to turn the transconductor ON and OFF, and thus a low-power LO buffer can be used to achieve wideband down-conversion. To further expand the bandwidth, the inductive peaking technique is used at the RF port to eliminate the capacitive loading effect resulted from the input transistors. As the noise power from LO stage appears in common mode at the mixer output, good noise performance is realized, too. Additionally, output distortion-cancellation IF buffer is added to facilitate the testing. Fabricated in the 0.13- $\mu \text{m}$ CMOS process, 15.5–17.5-dB gain and 4–5.2-dB noise figure are achieved in 1–10-GHz bandwidth. The mixer core consumes a low power of 8.3 mW from 1.5-V supply, and the whole chip consumes 22.3 mW, including the IF buffer. The active chip area is less than 0.2 mm2.

A +12-dBm OIP3 60-GHz RF Downconversion Mixer With an Output-Matching, Noise- and Distortion-Canceling Active Balun for 5G Applications

A CMOS millimeter-wave (mmWave) downconversion mixer with a local-oscillator (LO) buffer is proposed for wireless Gb/s data-transfer enabling systems, such as 5G systems. To obtain high linearity at low supply voltages, the proposed mmWave downconversion mixer adopts an on-chip transformer-based topology. In order to achieve differential to single-ended conversion and IF output matching, while maintaining a high linearity performance, the proposed mmWave downconversion mixer incorporates an active balun with common-source and common-drain configurations employing common-mode noise and third-order intermodulation distortion cancellations. The proposed downconversion mixer with active balun and LO buffer was implemented using a 65-nm CMOS process and it draws 18 mA from a 1 V supply voltage. It demonstrates a gain greater than 5.6 dB, noise figure less than 10.9 dB, and third-order output intercept point more than 12.4 dBm, in the band from 57 to 66 GHz.

Integrated CMOS RF transmitter with a single-ended power amplifier

This article presents a highly integrated CMOS RF double-sideband (DSB) transmitter (TX) including an active input balun and a single-ended power amplifier (PA) for a ultrahigh frequency radiofrequency identification (RFID) system-on-chip reader. The conventional TX architecture, including an up-conversion mixer and a balanced PA, requires an output balun to create the needed single-ended load. Compared to the conventional TX architecture, the proposed system provides a more compact circuit and uses a smaller chip area because the active balun and the single-ended PA have a much smaller size than those using a passive balun and a differential PA. In addition, the gain of the active balun, which is generally larger than unity, can be a benefit in the system design budget. The designed TX IC is fabricated using a 0.13 μm CMOS process on a small area of 780 × 560 μm2 (including pads). The TX IC exhibited an overall conversion gain of 41.7 dB, an output P1dB of 18 dBm, an OIP3 of 28 dBm, a DSB noise figure of 14.8 dB, and a power consumption of 284.4 mW, including the 42.9 mW consumed by the local oscillator buffer stages. The implemented TX IC complied with the spectral mask for the DSB amplitude-shift keying signal of the RFID reader at an output power of 15.5 dBm. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:205–210, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27257

Low-Power Sub-Harmonic Direct-Conversion Receiver With Tunable RF LNA and Wideband LO Generator at U-NII Bands

A low-power tunable-band sub-harmonic direct-conversion receiver covering the whole Unlicensed National Information Infrastructure band is demonstrated using 0.18-μm CMOS technology. The RF band is selected by tuning varactors at the loads of the two-stage low-noise amplifier, while a wideband octet- phase generator is applied at the local oscillator (LO) port. The band tuning of both an LC tank and a transformer and the de- sign of an optimal transformer turn ratio are fully discussed in this paper. Vertical-NPN bipolar junction transistors in a standard CMOS process are used at the mixer switching core for excellent 1/f noise performance. As a result, the receiver achieves a 48/50 voltage gain and 4.5/4.8-dB noise figure with a 1/f noise corner of 70 kHz when the RF band is tuned to 5.2/5.8 GHz, respectively. The dc current consumption of the RF front-end (including the LO buffer) is 8.5 mA at a 1.8-V supply.

A CMOS MedRadio Receiver RF Front-End With a Complementary Current-Reuse LNA

An ultra-low-power 401-406-MHz Medical Device Radiocommunications Service receiver RF front-end for biomedical telemetry applications is implemented using 0.18-μm CMOS technology. A single-ended complementary current-reuse low-noise amplifier (CCRLNA) is proposed that achieves a power gain of 20 dB, noise figure (NF) of 2.8 dB, IIP3 of -8.1 dBm, and second-order intercept point of +34 dBm while consuming only 150 μW at 1-V supply voltage. The total receiver RF front-end, including the proposed CCRLNA, in-phase/quadrature folded mixers, and local oscillator buffers, achieves a conversion gain of 28.7 dB, NF of 5.5 dB, and third-order intercept point of -25 dBm while consuming less than 500 μW from a 1-V supply voltage and occupying 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of core die area.

A 120–145 GHz Heterodyne Receiver Chipset Utilizing the 140 GHz Atmospheric Window for Passive Millimeter-Wave Imaging Applications

For passive mm-wave imaging applications, broadband mm-wave receivers functioning within atmospheric windows are highly desired. Within this paper, a heterodyne receiver chipset utilizing the 140 GHz atmospheric window is presented. The heterodyne chipset is based on two different millimeter-wave monolithic integrated circuits (MIMICs). One is the receiver MIMIC including a low-noise amplifier, a down-conversion mixer, a frequency multiplier and a local oscillator buffer amplifier together with a local oscillator distribution network. The other is a voltage-controlled oscillator (VCO) working in the 35 GHz frequency range to generate the local oscillator signal for the receiver (down-converter) chip. The process technology chosen to realize the chipset is a 100 nm gatelength metamorphic InAlAs/InGaAs high electron mobility transistor (HEMT) technology on 50 μm thick and 4 inch diameter GaAs substrates. The chips are utilizing a grounded coplanar waveguide (GCPW) technology. For an operation frequency band from 120 to 145 GHz, the receiver demonstrates a flat conversion gain between -1 and +2 dB with a power consumption of 120 mW. The VCO is tuneable from 31 to 37 GHz with associated output power levels from -2 to +1 dBm. Detailed descriptions of the individual building blocks are given and measured results are presented for the building blocks as well as for the receiver.

A dual-band direct-conversion RF front-end for WiMedia UWB receiver

This paper describes a direct-conversion RF front-end designed for a dual-band WiMedia UWB receiver. The front-end operates in band group BG1 and BG3 frequencies. It includes multi-stage LNAs, down-conversion mixers, a polyphase filter for quadrature local oscillator (LO) signal generation, and LO buffers. The UWB receiver is targeted for a mobile handset, where several other radios can be simultaneously on. Therefore, special attention was paid on minimizing the interference from different wireless systems. The front-end achieves approximately 26-dB gain and 4.9---5.6-dB noise figure (NF) across three sub-bands of BG1. In BG3 mode it obtains 23---26-dB gain and 6.9---7.7-dB NF. The front-end consumes 48.1 and 42.7 mA from a 1.2-V supply voltage in BG1 and BG3 operation modes, respectively. The chip was implemented in a 0.13-μm CMOS.

A 24-GHz CMOS Passive Subharmonic Mixer/Downconverter for Zero-IF Applications

The design and implementation of a 24-GHz subharmonic-mixer-based downconverter based on a multiphase local oscillator (LO) is presented. Fabricated in a 0.13-mum CMOS process, the downconverter includes a pre-amplifier and an IF buffer and consumes 14.4 mW from a 1.6-V supply. The quadrature LO buffer consumes 15 mA at 1.2 V. The circuit includes a single-ended to differential phase splitter for the LO. The downconverter has a conversion gain of 3.2 dB and double-sideband noise figure of 10 dB. The measured input referred 1-dB compression point is -12.7 dBm. DC offsets were less than 2 mV.

A CMOS multiphase shifting network with RC‐CR filter and bias‐level‐scaled active interpolator

AbstractA CMOS multiphase shifting network is described, which is developed for the use in a subharmonic mixing based direct‐conversion receiver of 5–6 GHz wireless LAN. Accurate phase shift and amplitude matching are simultaneously achieved with a third‐order RC–CR filter followed by the active interpolators whose bias levels are scaled for accurate phase shift. Implemented in a 0.18 μm CMOS process, the phase shifting network provides octa‐phase local oscillator (LO) signals spaced by 45°. The measured accuracy of the phase shift and amplitude matching are better than 0.8° and 0.4%, respectively. The phase shifting network excluding LO buffers dissipates 13 mW from a 1.8 V supply voltage. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 118–121, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22033