Local Memory Space Research Articles

Local Memory and Urban Space

The paper ponders over the issue of memory and urban space. It shows how these categories have been discussed in the literature and how they are connected to the problem of place identity. The paper also highlights the need to appreciate and assess the physical aspect of objects, which act as memory markers in the urban space. The author argues that what is being memorialised and conveyed as meaning is the past lived experience. As a case in point, two memory acts are analysed in the paper, clearly showing the interdependence of various temporalities in the anniversary celebrations. In the festivities celebrating the 100th (in 1881) and 150th (in 1931/2) anniversaries of the consecration of the Lutheran church in Warsaw, the capital of the Kingdom of Poland in the Russian partition and later the capital of a resurrected independent Polish state after 1918, the different present-oriented needs were mirrored in the narratives and commemorations of the past. Idiosyncratic visions of the past help make the small and vulnerable community of Lutherans in an otherwise primarily Roman Catholic environment more coherent, as its members may lay claim to history and construct and stabilise their identification process as descendants of past generations. Moreover, the material fabric of the church seems to be an indispensable factor. The parishioners’ lived experience appears to be a crucial component of commemorations in the late nineteenth and early twentieth centuries.

Research on parallel algorithm of high-power microwave devices simulation based on MPI-3

Simulation of high-power microwave source devices generally uses parallel algorithms to speed up the operation. In recent years, with the upgrade of parallel technology, the parallel efficiency of the particle simulation software has been further improved. Existing MPI-2 parallel technology of particle simulation software CHIPIC realizes the access to the local memory space of other processes through message passing. The new version of the MPI-3 standard provides the shared memory feature, which allows the data to be directly called by each process in the shared memory window, which reduces the information transmission. In this paper, based on the shared memory feature of MPI-3, the electromagnetic particle simulation parallel algorithm and dynamic load balancing algorithm are designed in the particle simulation software. The implementation of the two algorithms can improve the parallel efficiency from different aspects. The RKA and magnetic isolation oscillator high-power microwave devices are used as the test models. The test results show that the electromagnetic particle simulation parallel algorithm based on the shared memory feature of MPI-3 can improve the efficiency of the software by up to 44%. The efficiency of the dynamic load balancing algorithm based on MPI-3 can also be improved by up to 38%.

Efficient Online Classification and Tracking on Resource-constrained IoT Devices

Timely processing has been increasingly required on smart IoT devices, which leads to directly implementing information processing tasks on an IoT device for bandwidth savings and privacy assurance. Particularly, monitoring and tracking the observed signals in continuous form are common tasks for a variety of near real-time processing IoT devices, such as in smart homes, body-area, and environmental sensing applications. However, these systems are likely low-cost resource-constrained embedded systems, equipped with compact memory space, whereby the ability to store the full information state of continuous signals is limited. Hence, in this article,* we develop solutions of efficient timely processing embedded systems for online classification and tracking of continuous signals with compact memory space. Particularly, we focus on the application of smart plugs that are capable of timely classification of appliance types and tracking of appliance behavior in a standalone manner. We implemented a smart plug prototype using low-cost Arduino platform with small amount of memory space to demonstrate the following timely processing operations: (1) learning and classifying the patterns associated with the continuous power consumption signals and (2) tracking the occurrences of signal patterns using small local memory space. Furthermore, our system designs are also sufficiently generic for timely monitoring and tracking applications in other resource-constrained IoT devices.

Miradas para a Freguesia, participação social e a construção de valores na cidade

A Freguesia do Ó é hoje um importante referencial para entendermos a história da cidade de São Paulo a partir da perspectiva do crescimento urbano e dasociabilidade construída em uma ocupação além- Tietê. Essa é a frase de um texto produzido por uma arquiteta e urbanista, ou seja, como poderíamos iniciar a escrever sobre o bairro. No entanto, nossa proposta é apresentar diferentes vozes existentes sobre a Freguesia que encontraram no patrimônio um lugar comum. Juntos formamos um Grupo de Trabalho (GT) da Rede Paulista de Educação Patrimonial (Repep) que desde 2015 tem se reunido para a elaboração de ações educativas e propostas de valorização do patrimônio local, seja pela revisão do tombamento do bairro ou em defesa da constituição de um espaço de memória. Assim, produzimos textos sobre nossas relações com a Freguesia do Ó e como nos identificamos com esse patrimônio. No artigo, após introduzir o trabalho do GT, expomos os textos individuais na íntegra com a intenção de construir um diálogo escrito. Ainda que não representemos a totalidade dos diferentes sujeitos urbanos, esperamos demonstrar a potência de um trabalho produzido por meio da participação social, incluindo os diferentes significados e narrativas existentes no patrimônio da Freguesia do Ó.

Constant-Time Sliding Window Framework with Reduced Memory Footprint and Efficient Bulk Evictions

The fast evolution of data analytics platforms has resulted in an increasing demand for real-time data stream processing. From Internet of Things applications to the monitoring of telemetry generated in large data centers, a common demand for currently emerging scenarios is the need to process vast amounts of data with low latencies, generally performing the analysis process as close to the data source as possible. Stream processing platforms are required to be malleable and absorb spikes generated by fluctuations of data generation rates. Data is usually produced as time series that have to be aggregated using multiple operators, being sliding windows one of the most common abstractions used to process data in real-time. To satisfy the above-mentioned demands, efficient stream processing techniques that aggregate data with minimal computational cost need to be developed. In this paper we present the Monoid Tree Aggregator general sliding window aggregation framework, which seamlessly combines the following features: amortized $O(1)$ time complexity and a worst-case of $O(\log {n})$ between insertions; it provides both a window aggregation mechanism and a window slide policy that are user programmable; the enforcement of the window sliding policy exhibits amortized $O(1)$ computational cost for single evictions and supports bulk evictions with cost $O(\log {n})$ ; and it requires a local memory space of $O(\log {n})$ . The framework can compute aggregations over multiple data dimensions, and has been designed to support decoupling computation and data storage through the use of distributed Key-Value Stores to keep window elements and partial aggregations.

Lightweight Hardware Transactional Memory for GPU Scratchpad Memory

Graphics Processing Units (GPUs) have become the accelerator of choice for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. Using OpenCL terminology, GPUs offer a global memory space shared by all the threads in the GPU, as well as a local memory space shared by only a subset of the threads. Programmers can use local memory as a scratchpad to improve the performance of their applications due to its lower latency as compared to global memory. In the SIMT execution model, data locking mechanisms used to protect shared data limit scalability. To take full advantage of the lower latency that local memory affords, and to provide an efficient synchronization mechanism, we propose GPU-LocalTM as a lightweight and efficient transactional memory (TM) for GPU local memory. To minimize the storage resources required for TM support, GPU-LocalTM allocates transactional metadata in the existing memory resources. Additionally, GPU-LocalTM implements different conflict detection mechanisms that can be used to match the characteristics of the application. For the workloads studied in our simulation-based evaluation, GPU-LocalTM provides from 1.1X up to 100X speedup over serialized critical sections.

The Brazilian Institute of Architects – the establishment of Sa?o Paulo Chapter and the construction of its headquarters

The purpose of this article is to rescue, through documentary re- search, the establishment of the Brazilian Institute of Architects in Sa?o Paulo (IAB/SP) and the construction of its headquarters in the city, one of the leading examples of modern architecture, as well as the integration of architecture and other arts. First located in the basement of a modern building called Esther, its design, ob- ject of a contest, situated in the corner of Bento Freitas and Gene- ral Jardim Street, at Vila Buarque, had as winners and authors of the nal project the architects Abelardo Reidy de Souza, Galiano Ciampaglia, He?lio Queiroz Duarte, Jacob Ruchti, Miguel Forte, Rino Levi, Roberto de Cerqueira Ce?sar and Zenon Lotufo. It was built in the 1950’s, in a region that became a new urban center of cultural and artistic activities with new museums, libraries, cinemas, thea- ters, art galleries and bookshops and IAB/SP joined these spaces. As the building became part of a network of sociability among architects and other artists, it was possible to spread the values of the architects’ profession. Many politicians, young students, tea- chers, intellectuals and artists used and visited the building during exhibitions, music auditions, lectures and other events promoted by the Institute. Moreover, as a space of ideological exchanges, in 1964 with the Military Coup it became a symbolic site of struggle for freedom. Protected by the State Heritage body – CONDEPHAAT (Council for the Defense of the Historical, Archeological, Artistic and Touristic Heritage) in 2020, and in 2015 by CONPRESP (Sa?o Paulo City Council for the Preservation of Historical, Cultural and Environmental Patrimony) and IPHAN (Institute of National His- torical and Artistic Heritage), its restoration process predicted beyond the recovery of the physical structure of the building, the fac?ade restoration and the improvements in the use of some spa- ces. The renovation started and was partially completed, focusing on the structure of the external marquise and the reestablishment of the events space of the Institute, that returned to host events. Gradually, the street in which it is located has resumed its centra- lizing process of activities carried out by architects in the region. New young architects chose the same street for their o ces and a specialized architecture bookstore was installed on the ground oor of IAB/SP building. These spaces were a de nite boost to the resumption of the IAB/SP building as an important model of modern architecture in Sa?o Paulo, a local memory space and re- presentative of this professional segment.

Many-Core Real-Time Task Scheduling with Scratchpad Memory

This work is motivated by the demand for scheduling tasks upon the increasingly popular island-based many-core architectures. On such an architecture, homogeneous cores are grouped into islands, each of which is equipped with a scratchpad memory module (referred to as local memory). We first show the NP-hardness and the inapproximability of the scheduling problem. Despite the inapproximability, positive results can still be found when different cases of the problem are investigated. A $(3-\frac{1}{F})$ - approximation algorithm is proposed for the minimization of the maximum system utilization, where $F$ is the number of cores in the platform. When the technique of resource augmentation is considered, this paper further develops a $(\gamma +1)$ -memory $\frac{2\gamma -1}{\gamma -1}$ -approximation algorithm, where $\gamma$ represents the trade-off between CPU utilization and local memory space. On the other hand, a special case is also considered when the ratio of the worst-case execution time of a task without and with using the local memory is bounded by a constant. The capabilities of the proposed algorithms are then evaluated with benchmarks from MRTC, UTDSP, NetBench and DSPstone, where the maximum system utilization can be significantly reduced even when the local memory size is only 5 percent of the total footprint of all of the tasks.

Поддержка стандарта OpenMP 4.0 для архитектуры NVIDIA PTX в компиляторе GCC

The paper describes the approach used in implementing OpenMP offloading to NVIDIA accelerators in GCC. Offloading refers to a new capability in OpenMP 4.0 specification update that allows the programmer to specify regions of code that should be executed on an accelerator device that potentially has its own memory space and has an architecture tuned towards highly parallel execution. NVIDIA provides a specification of the abstract PTX architecture for the purpose of low-level, and yet portable, programming of their GPU accelerators. PTX code usually does not use explicit vector (SIMD) computation; instead, vector parallelism is expressed via SIMT (single instruction - multiple threads) execution, where groups of 32 threads are executed in lockstep fashion, with support on hardware level for divergent branching. However, some control flow constructs such as spinlock acquisition can lead to deadlocks, since reconvergence points after branches are inserted implicitly. Thus, our implementation maps logical OpenMP threads to PTX warps (synchronous groups of 32 threads). Individual PTX execution contexts are therefore mapped to logical OpenMP SIMD lanes (this is similar to the mapping used in OpenACC). To implement execution of one logical OpenMP thread by a group of PTX threads we developed a new code generation model that allows to keep all PTX threads active, have their local state (register contents) mirrored, and have side effects from atomic instructions and system calls such as malloc happen only once per warp. This is achieved by executing the original atomic or call instruction under a predicate, and then propagating the register holding the result using the shuffle exchange (shfl) instruction. Furthermore, it is possible to setup the predicate and the source lane index in the shuffle instruction in a way that this sequence has the same effect as just the original instruction inside of SIMD regions. We also describe our implementation of compiler-defined per-warp stacks, which is required to have per-warp automatic storage outside of SIMD regions that allows cross-warp references (normally automatic storage in PTX is implemented via .local memory space which is visible only in the PTX thread that owns it). This is motivated by our use of unmodified OpenMP lowering in GCC where possible, and thus using libgomp routines for entering parallel regions, distribution of loop iterations, etc. We tested our implementation on a set of micro-benchmarks, and observed that there is a fixed overhead of about 100 microseconds when entering a target region, mostly due to startup procedures in libgomp (and notably due to calls to malloc), but for long-running regions where that overhead is small we achieve performance similar to analogous OpenACC and CUDA code.

Real-Time Task Scheduling on Island-Based Multi-Core Platforms

With the increasing number of cores in a computing system, how to coordinate the computing units and heterogeneous memory resources has soon become extremely critical for real-time systems. This paper explores the joint considerations of memory management and real-time task scheduling over island-based multi-core architecture, where the local memory module of an island offers shorter access time than the global memory module does. The objective of this work is to minimize the number of needed islands to successfully schedule real-time tasks. When the required amount of the local memory space is specified for each task, a scheduling algorithm is proposed to provide an asymptotic 299-approximation bound. When there is flexibility in determining the needed local memory space for each task, we propose an algorithm with an asymptotic 4-approximation bound to jointly manage memory resources and allocate computing cores. In addition to the worst-case approximation analysis, the proposed algorithms are also evaluated with 82 real-life benchmarks with the support of a worst-case execution time analyzer. Moreover, extensive evaluations are conducted to show the capability of the proposed approaches when being used with various computing cores and memory resources.

Autonomous L3 Cache Technolgy for High Responsiveness

Web services and cloud computing paradigms have opened up many new vistas. The data intensive cloud applications usually require huge amounts of data to input and output from secondary storage systems. The outstanding progress in area of network communications has enabled high speed networks and therefore, communication latency bottleneck in cloud and other web applications has been shifted to node/storage level. Moreover, existing cloud solutions focused mainly on the efficient utilization of computing resources through virtualization and issues of storage bottleneck did not receive much attention. Moreover, virtualization based implementation ensures equal priority to all hosted applications, thus, real time applications in cloud environment can't meet their requirements. To meet the demand of overall low latency in cloud and other web services; and particularly to reduce I/O bottleneck at storage level, novel idea of autonomous L3 cache technology is proposed. Autonomous L3 cache technology utilizes local memory space as dedicated block device cache for certain specific application, thus prioritizing it over rest of hosted ones. Evaluation shows performance improvement of 5-8 times in terms of timeliness in given setup.