Local Common-mode Feedback Research Articles

A local positive feedback loop-reused technique for enhancing performance of folded cascode amplifier

A current-reused folded cascode operational transconductance amplifier (OTA) using a local positive feedback (LPFB) technique has been proposed in previous literature, which does not achieve maximum unity gain-bandwidth (GBW). Besides, the stability of LPFB in the LPFB-OTA is limited by local common mode feedback (LCMFB) resistors. Based on the analysis, a local positive feedback loop-reused (LPFBR) technique is proposed to improve the performance of conventional LPFB OTA. For a fair comparison, both conventional and proposed OTAs working at saturation region are designed and simulated in SMIC 0.18μm process. The simulated results demonstrate that the proposed LPFBR-OTA has almost 10.5 times the bandwidth and maintains stability compared to that of the conventional LPFB-OTA under the condition that LCMFB resistors are increased by a factor of 10.

16.2-μW Super Class-AB OTA with current-reuse technique achieving 130.3-μA/μA FoM

In this paper, a single-stage Super Class-AB operational transconductance amplifier (OTA) using current reuse technique is presented. It is based on two scaled current mirrors located at the tail current nodes of input pairs, reusing the current through the cross-coupled input pairs by a current gain factor of α, and delivering new currents to the output branch, enhancing the overall transconductance (Gm) by a factor of (1+α). With adaptive biasing and local common mode feedback (LCMFB), slew rate (SR), open loop gain (AOL) and gain-bandwidth product (GBW) are improved. An prototype has been designed in TSMC 0.18-μm CMOS process. Post-simulation shows the positive and negative slew rate of 22V/μs and −38.3V/μs, respectively, a GBW of 3.72 MHz, a DC gain of 65.6 dB with a phase margin of 69.2° for a capacitive load of 70 pF. The proposed OTA consumes a total power of 16.2 μW under a 1.8V supply voltage.

A high current efficiency rail-to-rail operational amplifier

ABSTRACT This paper proposes a new single stage high current efficiency rail to rail amplifier (HCE-RTR). Due to the combination of a new constant transconductance control circuit and local common mode feedback (LCMFB) technique, the proposed rail to rail amplifier not only achieves improvements in unity-gain bandwidth (GBW) and slew rate (SR), but also ensures input stage transconductance constancy within the rail to rail voltage range. Based on the SMIC 180 nm process, the post-layout simulation results show that the proposed amplifier achieves rail-to-rail input/output. The simulated open loop AC response shows the DC gain, GBW, and PM are 66.2 dB, 8.2 MHz, and 60.97 o , respectively. When the driving load capacitance is 70 pF, the transient response simulation results show that the proposed amplifier achieves 0.039 µs average 1% settling time, and about 5.73 V/µs average slew rate. Note that under the condition of 1.8 V power supply, the power consumption is only 122.4 µW, proving the proposed amplifier can achieve high current efficiency while maintaining stability.

±0.15 V three‐stage bulk‐driven AB OTA with 36 MHzpF/µW and 55(V/µs)pF/µW small and large‐signal figures of merit

AbstractA three‐stage rail‐to‐rail bulk‐driven class AB OTA that operates with ±0.15 V supplies and a power dissipation of 90 nW is introduced. The first two stages use resistive local common mode feedback. The OTA uses simple phase lead compensation. It has a 36 MHz.pF/μW small signal figure of merit and a 55(V/μs) pF/μW large signal figure of merit.

A Review of Techniques to Enhance an Amplifier’s Performance Using Resistive Local Common Mode Feedback

A review of some of the most common applications of the resistive local common mode feedback technique to enhance amplifier’s performance is presented. It is shown that this simple technique offers essential improvement in open loop gain, gain-bandwidth product, slew rate, common mode rejection ratio, power supply rejection ratio, etc. This is achieved without increasing power dissipation or supply voltage requirements and with small additional silicon area and circuit complexity. It is also shown that it is especially appropriate to improve amplifiers’ performance in current fine-line submicrometer CMOS technology. Some of the applications discussed are GB enhanced, class AB and super class AB operational amplifiers, gain boosted op-amps, bulk-driven circuits, sample and hold circuits and power management circuits, among others.

Simple Technique to Improve Essentially the Performance of One-Stage Op-Amps in Deep Submicrometer CMOS Technologies

A comparative study of one-stage-amp performance improvement based on simulations in 22 nm, 45 nm, 90 nm, and 180 nm in deep submicrometer CMOS technologies is discussed. Generic SPICE models were used to simulate the circuits. It is shown that in all cases a simple modification using resistive local common mode feedback increases open-loop gain and gain-bandwidth product, peak output currents, and slew rate by close to an order of magnitude. It is shown that this modification is especially appropriate for its utilization in current CMOS technologies since large factor improvements were not available in previous technologies. The OTAs with resistive local common mode feedback require simple phase lead compensation with a very small additional silicon area and keep supply requirements and static power dissipation unchanged.

A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations

This paper presents a novel 0.3V rail-to-rail body-driven three-stage operational transconductance amplifier (OTA). The proposed OTA architecture allows achieving high DC gain in spite of the bulk-driven input. This is due to the doubled body transconductance at the first and third stages, and to a high gain, gate-driven second stage. The bias current in each branch of the OTA is accurately set through gate-driven or bulk-driven current mirrors, thus guaranteeing an outstanding stability of main OTA performance parameters to PVT variations. In the first stage, the input signals drive the bulk terminals of both NMOS and PMOS transistors in a complementary fashion, allowing a rail-to-rail input common mode range (ICMR). The second stage is a gate-driven, complementary pseudo-differential stage with an high DC gain and a local CMFB. The third stage implements the differential-to-single-ended conversion through a body-driven complementary pseudo-differential pair and a gate-driven current mirror. Thanks to the adoption of two fully differential stages with common mode feedback (CMFB) loop, the common-mode rejection ratio (CMRR) in typical conditions is greatly improved with respect to other ultra-low-voltage (ULV) bulk-driven OTAs. The OTA has been fabricated in a commercial 130nm CMOS process from STMicroelectronics. Its area is about 0.002 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mm</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and power consumption is less than 35nW at the supply-voltage of 0.3V. With a load capacitance of 35pF, the OTA exhibits a DC gain and a unity-gain frequency of about 85dB and 10kHz, respectively.

High current efficiency fast transient gain-boosted single-stage bulk-driven OTA with enhanced input stage suitable for heavy capacitive loads

This article presents a 0.5 V operated, bulk-driven subthreshold OTA with up to 30 nF capacitive load driving capability. The input stage utilizing three unmatched pseudo-differential pairs is biased with two DC level shifters, especially bulk-driven flipped voltage followers in a direct and cross-coupled connection, exhibiting superior performance to existing bulk-driven OTAs. The input transconductance stage with local common-mode feedback (LCMFB) followed by partial positive feedback (PPF) contributes a large dynamic output current using three-successive amplification. As a result, the proposed OTA provides 24.2 times higher effective input core transconductance, 2.62 times higher DC gain, and 11.5 times more slew rate than a conventional class-A BD OTA with PPF at 5% lower static power. The post-layout results of the proposed OTA for a 10 nF capacitive load using UMC 0.18-µm technology in Cadence Virtuoso-XL yield a DC gain of 124.6 dB, a UGF of 183.47 kHz, a PM of 89.98°, and greater figures of merit (FOM) for small- and large-signal performance than the state-of-the-art bulk-driven OTAs.

An ultra high slew rate recycling folded cascode OTA with 100-dB DC gain

This article presents an operational transconductance amplifier (OTA) with enhanced transconductance and slew rate. High transconductance is achieved by implementing local common-mode feedback (LCMF) in a new path. This new path also is used in providing the current splitting technique. The slew rate is significantly boosted due to a new slew rate enhancement circuit, a new quasi-floating gate (QFG) circuit and two non-linear current mirrors. The advantage of the proposed OTA is that its large-signal and small-signal figures of merits are remarkably improved compared to previous works. The post-layout simulation of the OTA is in TSMC 180 nm CMOS process. Monte Carlo and corner analyses shows the robustness of the OTA with variations of process and mismatch.

A capless NMOS low-dropout regulator with 15 ns transient response time

In this paper, a fast-transient capless NMOS low-dropout regulator (LDO) with low power consumption is proposed. The capacitor multiplier and Super Class-AB operational transconductance amplifier (OTA) with local common mode feedback structure (LCMFB) is employed in the proposed LDO, which not only consumes a small quiescent current but also greatly improves the transient response by increasing the loop bandwidth and charging/discharging current at the gate of the power transistor. Meanwhile, excellent line/load regulation is also achieved by the proposed LDO. The proposed capless LDO was implemented in 0.18 μm CMOS process and the post-layout simulation results show that the transient response of recovery time is only 15 ns, low quiescent current is 11 μA, and line regulation and load regulation are 0.61 mV/V and 7.58 μV/mA respectively.

Fully Differential Miller Op-Amp with Enhanced Large- and Small-Signal Figures of Merit

A highly power-efficient, fully differential Miller op-amp with accurately controlled output quiescent current is introduced. The op-amp can drive both capacitive and resistive load due to the presence of the auxiliary amplifier. This amplifier helps to achieve class AB operation of the proposed op-amp. The fully differential auxiliary amplifier is compact and uses a resistive local common-mode feedback network. It consumes only 6% of the total current of the op-amp. The proposed op-amp has several innovative features. Incorporating the auxiliary amplifier helps to improve the unity gain frequency, power efficiency, slew-rate, and common-mode rejection ratio of the proposed op-amp. It can drive a wide range of resistive (200 Ω–1 MΩ) and capacitive loads (5 pF–300 pF). The op-amp has a large signal dynamic current efficiency of 8.6 and a large signal static current efficiency of 7.9. The small-signal figure of merit is 8.7 for RL = 1 MΩ and 7.3 for RL = 200 Ω.

An Ultra-Low-Voltage class-AB OTA exploiting local CMFB and Body-to-Gate interface

In this work a novel bulk-driven (BD) ultra-low-voltage (ULV) class-AB operational transconductance amplifier (OTA) which exploits local common mode feedback (LCMFB) strategies to enhance performance and robustness against process, voltage and temperature (PVT) variations has been proposed. The amplifier exploits body-to-gate (B2G) interface to increase the slew rate and attain class-AB behaviour, whereas two pseudo-resistors have been employed to increase the common mode rejection ratio (CMRR). The architecture has been extensively tested through Monte Carlo and PVT simulations, results show that the amplifier is very robust in terms of gain-bandwidth-product (GBW), power consumption and slew rate. A wide comparison against state-of-the-art has pointed out that best small-signal figures of merit are attained and good large-signal performance is guaranteed, also when worst-case slew rate is considered.

Implementation of Power-Efficient Class AB Miller Amplifiers Using Resistive Local Common-Mode Feedback

An approach to implement single-ended power-efficient static class-AB Miller op-amps with symmetrical and significantly enhanced slew-rate and accurately controlled output quiescent current is introduced. The proposed op-amp can drive a wide range of resistive and capacitive loads. The output positive and negative currents can be much higher than the total op-amp quiescent current. The enhanced performance is achieved by utilizing a simple low-power auxiliary amplifier with resistive local common-mode feedback that increases the quiescent power dissipation by less than 10%. The proposed class AB op-amp is characterized by significantly enhanced large-signal dynamic, static current efficiency, and small-signal figures of merits. The dynamic current efficiency is 15.6 higher, the static current efficiency is 10.6 times higher, and the small-signal figure of merit is 2.3 times higher than the conventional class-A op-amp. A global figure of merit that determines an op-amp’s ultimate speed is 6.33 times higher than the conventional class A op-amp.

Low-power LDO Design of High-efficiency Class AB OTA Based on Adaptive Biasing

This design proposes a new low-dropout linear regulator (LDO) with low input voltage and low standby power consumption. A new type of adaptive bias circuit is proposed, which uses a high-efficiency class AB OTA based on class AB differential input stage and local common mode feedback (LCMFB), which not only increases the gain bandwidth product (GBW), but also improves current efficiency, in addition, a dynamic charging transistor (DCT) is used to enhance the transient characteristics of the circuit. The circuit design uses 0.18μm standard CMOS technology to achieve a stable output of 1.0V after the power supply voltage is adjusted from 1.2V, and the maximum output current is 100mA. The quiescent current is only 2.3μA at no-load, when the load current is converted from 1mA to 100mA within 1μs, the overcharge voltage is less than 130mV, and the full range of load current stability from 1mA to 100mA is achieved under the maximum 100pF load capacitor.

Super-Gain-Boosted AB-AB Fully Differential Miller Op-Amp With 156dB Open-Loop Gain and 174MV/V MHZ pF/μW Figure of Merit in 130nm CMOS Technology

A fully differential Miller op-amp with a composite input stage using resistive local common-mode feedback and regulated cascode transistors is presented here. High gain pseudo-differential auxiliary amplifiers are used to implement the regulated cascode transistors in order to boost the output impedance of the composite input stage and the open-loop gain of the op-amp. Both input and output stages operate in class AB mode. The proposed op-amp has been simulated in a 130nm commercial CMOS process technology. It operates from a 1.2V supply and has a close to rail-to-rail differential output swing. It has 156dB DC open-loop gain and 63MHz gain-bandwidth product with a 30pF capacitive load. The op-amp has a DC open-loop gain figure of merit $FOM_{AOLDC}$ of 174 (MV/V) MHz pF/ $\mu \text{W}$ and large-signal figure of merit $FOM_{LS} $ of 3(V/ $\mu \text{s}$ ) pF/ $\mu \text{W}$ .

Low quiescent current capacitor-less LDO regulator with high slew rate super class AB CMOS OTA

This paper presents a low quiescent current capacitor-less low-dropout regulator (LDO) with high slew rate super class AB CMOS operational transconductance amplifier (OTA). The OTA of this design is based on the combination of class AB differential input stages and local common-mode feedback (LCMFB) which provides additional dynamic current boosting, increased gain-bandwidth (GBW) product and slew rate (SR). LCMFB is applied to various class AB differential input stages, leading to different class AB OTA topologies. The design also uses dynamic charging transistor (DCT) to enhance the transient characteristics of the circuit. The presented LDO is fabricated in a 0.18 um standard CMOS process. The circuit consumes a quiescent current of 10 uA at no load, regulating the output at 1.0V with maximum output current of 100mA from a voltage supply of 1.2V. It achieves full range stability from 1mA to 100mA load current at a maximum 100pF load capacitor.

Pseudo-Three-Stage Miller Op-Amp With Enhanced Small-Signal and Large-Signal Performance

A simple technique to implement highly power efficient class AB–AB Miller op-amps is presented in this paper. It uses a composite input stage with resistive local common mode feedback that provides class AB operation to the input stage and essentially enhances the op-amp’s effective transconductance gain, the dc open-loop gain, the gain-bandwidth product, and slew rate with just moderate increase in power dissipation. The experimental results of op-amps in strong inversion and subthreshold fabricated in a 130-nm standard CMOS technology validate the proposed approach. The op-amp has $9~\text {V} \cdot \text {pF}/\mu \text {s}\cdot \mu \text{W}$ large-signal figure of merit (FOM) and $17~\text {MHz}\cdot \text {pF}/\mu \text{W}$ small-signal FOM with 1.2-V supply voltage. In subthreshold, the op-amp has $10~\text {V}\cdot \text {pF}/\mu \text {s}\cdot \mu \text{W}$ large-signal FOM and $92~\text {MHz}\cdot \text {pF}/\mu \text{W}$ small-signal FOM with 0.5-V supply voltage.

Stimulation and Artifact-Suppression Techniques for In Vitro High-Density Microelectrode Array Systems.

We present novel voltage stimulation buffers with controlled output current, along with recording circuits featuring adjustable high-pass cut-off filtering to perform efficient stimulation while actively suppressing stimulation artifacts in high-density microelectrode arrays. Owing to the dense packing and close proximity of the electrodes in such systems, a stimulation through one electrode can cause large electrical artifacts on neighboring electrodes that easily saturate the corresponding recording amplifiers. To suppress such artifacts, the high-pass corner frequencies of all available 2048 recording channels can be raised from several Hz to several kHz by applying a "soft-reset" or pole-shifting technique. With the implemented artifact suppression technique, the saturation time of the recording circuits, connected to electrodes in immediate vicinity to the stimulation site, could be reduced to less than 150 μs. For the stimulation buffer, we developed a circuit, which can operate in two modes: either control of only the stimulation voltage or control of current and voltage during stimulation. The voltage-only controlled mode employs a local common-mode feedback operational transconductance amplifier with a near rail-to-rail input/output range, suitable for driving high-capacitive loads. The current/voltage controlled mode is based on a positive current conveyor generating adjustable output currents, whereas its upper and lower output voltages are limited by two feedback loops. The current/voltage controlled circuit can generate stimulation pulses up to 30 μA with less than ±0.1% linearity error in the low-current mode and up to 300 μA with less than ±0.2% linearity error in the high-current mode.

Super class AB RFC OTA with adaptive local common‐mode feedback

A super class AB recycling folded cascode operational transconductance amplifier is presented. It employs local common-mode feedback using two matched tuneable active resistors, allowing to adapt the amplifier to different process variations and loads. Measurement results from a test chip prototype fabricated in a 0.5 μm CMOS process validate the proposal.

Super class AB RFC OTA using non‐linear current mirrors

An alternative approach to the design of super class AB recycling folded cascode operational transconductance amplifiers is proposed. Instead of using local common-mode feedback for boosting dynamic currents, simple current mirrors with input transistors entering triode region for large currents are employed. Measurement results from a 0.5 μm CMOS test chip validate the proposal.