Load Board Research Articles

A Dual-Band Dual-Polarized 2x2 Antenna Array with Beamforming for 5G AiP and mmWave Applications

In this study, we present a dual-band (28/39GHz) 2 by 2 antenna array design on a 10(4+2+4) multi-layer organic substrate with broad bandwidth and higher isolation onto a compact AiP module. In addition, the H-type slot antenna structure can improve interference and isolation between 28 and 39GHz bands. The measured result shows the isolation can larger than 15dB between low and high band. For antenna measurement, the spherical of probing chamber is utilized to validate 28/39GHz antenna pattern and performance with a package level passive testing. Our AiP measured result shows the return loss is better than 10 dB in 23.5-30.5 GHz range, with ~7 GHz bandwidth and provides a high-gain per element (above ~6 dBi) radiation pattern for 28GHz applications. For 39GHz band, the antenna has 7 GHz bandwidth and provides a 5 dBi gain between 38-45 GHz. Comparison of S-parameter between simulated and measured results, there is a good correlation to obtain the quality of manufacturing. Furthermore, a 28GHz beamforming array is designed and demonstrated. The beamfoming array consists of a four-channel transceiver with 2 x 2 antenna array. The beamformer IC is implemented by TSMC 90-nm CMOS technology and the flip-chip bonded on BT substrate. For beamforming test, an integrated socket and load board are designed for support the mmWave module and then connection between DUT and test system. The load board substrate includes the IF, LO, and DC distribution network for respectively. There are 4-channel transmit beamforming array front-end module for testing. Finally, the 3D beam steering of 2 by 2 antenna array is measured with multi-states at 28 GHz, with a maximum realized gain of 11.8 dBi achieved in the main beam (θ=0°). It shows that beamforming can be generated at a specific beam direction by controlling the phase of the signal in each antenna element.

Coverage and reliability improvement of copper metallization layer in through hole at BGA area during load board manufacture

Abstract The dimple of ball grid array (BGA) area with 70 mm × 70 mm size on load board for high performance integrated circuit final test is investigated by shadow moire at first, the dimple of BGA area decreases from 184.3 to 97.1 μm when six additional prepregs with 60 mm × 60 mm size are added at BGA area before hot lamination process. The micromorphology and stress/strain simulation are conducted to improve the coverage and reliability of copper metallization layer in through hole at that BGA area. The microcracks of electroless copper layer at the position of glass fiber and inner layer copper pad, which leads to serious crack after solder float, are well covered by subsequent electroplating copper layer. When the through holes at BGA area with 0.2 mm diameter and 7.0 mm depth are fabricated based on insulating dielectric material used for high-speed signal transmission, the simulation results point out that IT968 is better than M6G for the thermal shock reliability of through hole metallization layer. A load board vehicle with 126 layers and 8.3 mm thickness based on IT968 shows good interconnection structure reliability after 12 times 288°C solder float.

Truck Hall: riding with the tide

Learning outcomes Upon completion of the case study, students should be able to understand how changes in a macro environment affect the competitive landscape in an emerging market; acquire a granular understanding about the logistics industry in an emerging market and the various business models developed to service customer needs; determine the attractiveness and challenges of doing business in a fragmented but sunrise industry in an emerging market; and identify the drivers for growth and profitability in the logistics business. Case overview/synopsis Manisha Sharaf (she/her) and her co-founders conceived the idea of Truck Hall in 2011 to ride with the tide created by booming public investments in the infrastructure and transportation sector. Truck Hall aimed to improve the efficiency of the logistics industry in India by extensively using technology. However, the market research showed that technology-driven services in logistics faced many challenges owing to low internet penetration in the country, weak network connectivity during transportation and the low literacy rates of the truck drivers who were central to this industry. Between 2015 and 2018, Truck Hall experimented with several business models including load board, brokerage and integrated transporter with the sole purpose of achieving profitable growth in a highly fragmented industry with razor-thin margins. This case documented the dilemma faced by a startup in a high-growth but largely unorganized and unregulated industry in a developing economy. Should Truck Hall continue with the current business model of being a niche player or should it vertically integrate and control major segments of the value chain? Should it compromise on growth to become profitable or first scale up? Complexity academic level This case study can be used at the undergraduate, graduate and executive levels. Supplementary materials Teaching notes are available for educators only. Subject code CSS 11: Strategy.

Built-in Harmonic Prediction Scheme for Embedded Segmented-Data-Converters

Increase in manufacturing test cost is of paramount issue to chip suppliers, which has been primarily due to costly external testers and long test-time. This paper proposes a loopback-based self-test technique to cost-effectively predict the dynamic nonlinearities of on-chip segmented digital-to-analog-converter (DAC) and analog-to-digital-converter (ADC), by externally looping a DAC back to an ADC, through an external load board employing two parallel paths: a programmable-gain-amplifier (PGA) path and a bypass path for test purpose. A segmented DAC (or ADC) consists of coarse and fine DACs (or ADCs). Two loopback tests are sequentially performed. For the first loopback test, a clean and single-tone sinusoidal signal is applied to a coarse DAC, and it bypasses a fine DAC for test purpose. The obtained DAC output is then fed to a coarse ADC through a bypass path on the load board. Simultaneously, the DAC output is applied to a fine ADC through a PGA path, so that the DAC output signal can fit into the input full-scale range of the fine ADC. For the second loopback test, a sinusoid is fed to a fine DAC, and it bypasses a coarse DAC in this time. Similarly, the DAC output is then applied to a fine and a coarse ADCs through two paths on the load board, at the same time. For postprocessing in on-chip processor, the correlation equations between the dynamic nonlinearities of sub-DACs/ADCs and the aforementioned loopback responses are simultaneously solved to predict the dynamic nonlinearity for each of a DAC and an ADC. Simulation and hardware measurements verified that the proposed technique can be practically used for production testing, by showing less than 0.28-dB and 0.55-dB of the prediction errors, respectively.

Smart Grid Control System using Solar Panel

As the technology grows very fast, we need more and more power so one of the ultimate choices is renewable energy. Solar energy is the best one among all types of renewable energy. This paper presents a smart grid control system using solar energy. Here, the smart grid control system consists of source board, control board, Arduino board and load board. The solar panel is the source which provides input energy to the control system. The control board composed of relay, operational amplifier (OPAMP) and the bipolar junction transistor (BJT).An interface with Arduino board is done to take inputs and give controlled output, further; we can use battery for storing our solar power and can be reusable by the load which will again enhance our solar power usability. Sunlight based solar panel gives cost investment funds by not paying for power, particularly for power costs keep on rising where the expense of sun oriented keeps on falling. Cost reserve funds likewise can be determined by wiping out the need to channel in framework control, upsetting encompassing scenes and hardscapes, fixing zones, and so on.

Analysis to Evolution of Numerical Simulation to the Whole Process of Destroy for Main Arch of Stone Arch Bridge

6m arch board used as test object, this paper introduces the arch in different level of load board cracks, development and production of plastic hinge until the whole process for all the damage simulation numerical simulation analysis then compared with experimental results and analysis of increased with load crack distribution, which can be used to understand the similar in service work condition of the stone bridge.

Phase Distortion to Amplitude Conversion-Based Low-Cost Measurement of AM-AM and AM-PM Effects in RF Power Amplifiers

This work develops a simple, practical yet easily realizable method for low cost measurement of phase and amplitude distortions in radio frequency power amplifiers (RF PA). Amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortions are two significant distortion effects in PAs at high output power levels, causing out of band interference in the transmitted signal and bit errors in the received signal. Traditional measurements of amplitude and phase distortion in RF PAs require the use of expensive vector network analyzers. In this work, we propose the use of phase-to-amplitude conversion to develop a low cost and accurate test methodology for AM-AM and AM-PM measurement using simple load board test circuitry along with software based difference generation and peak detection mechanisms. Using either simple sine wave stimulus with power sweep or a single amplitude modulated RF stimulus, both distortion effects can be measured with high accuracy for nominal devices as well as over process and voltage variations, while allowing significant reduction in test cost.

Phase-Aware Multitone Digital Signal Based Test for RF Receivers

This paper presents a method for testing RF receivers that utilizes a multitone digital signal generation scheme and relies on the analysis of the receiver baseband output to compute the RF performance parameters. The proposed method eliminates the cost of expensive RF instrumentation on the input side of receiver testing and only requires low-cost on-chip baseband digitization at the output of the receiver. The complexity of the RF signal generation inherent to standard methods is traded off with extensive signal processing in the baseband. The analysis necessary for tackling the problem of extracting RF metrics is addressed and presented herein. Whereas the proposed test scheme was implemented and experimentally verified on a load board for testing UHF receivers, generalized use in BIST applications in need of multi-GHz RF stimuli is also discussed in the paper. RF performance parameters like Gain, Noise Figure (NF), and IIP3 were simulated and measured using both standard methods and the proposed method and, the results are shown to be accurate to within 0.5 dB for Gain and 1 dB for NF and IIP3.

Test Signal Development and Analysis for OFDM Systems RF Front-End Parameter Extraction

Testing radio frequency (RF) transceivers requires the measurement of a diverse set of specifications, requiring multiple testing setups. This complicates load board design, debug, and diagnosis, as well as results in long testing time. In this paper, we present a single setup testing solution for orthogonal frequency-division multiplexing systems RF front-ends based on a loop-around scheme. With this technique, it is possible to determine gain and phase mismatch, inphase-quadrature time skew, and dc offset. Linear gain and IIP3 decouple the transmitter parameters from the receiver parameters. Although loop-around has been used in many forms, the basic challenge is to determine what input conditions will lead to accurate measurement and what form of modeling will yield this accuracy. To this end, we develop test signal design and multistep extraction techniques. Experimental results indicate that IIP3 can be extracted with 0.6 dB maximum error while phase mismatch and gain mismatch can be extracted with 0.3° and 0.6% maximum error. Our method is able to de-embed the characteristics of transmitter from those of receiver while it requires the analysis of only low-frequency digital baseband signals (I and Q branches) and eliminates the need for RF testers.

FPGA based chip emulation system for test development of analog and mixed signal circuits: A case study of DC–DC buck converter

Prototyping on FPGA has become a main stream verification methodology for hardware design, test development, software co-design, etc. in the area of digital VLSI. In the case of test development, FPGA serves as a virtual DUT (Design Under Test) and test patters are applied from automatic test equipment (ATE). This verifies not only the chip with design for test (DFT) circuitry and test program but also the entire test setup involving virtual DUT, load board, interconnections with ATE, etc. Although, FPGA based platform is used widely for test program verification of digital ICs, this technique is not used for analog/mixed signal (AMS) circuits because of the difficulty in implementing AMS circuits in FPGAs. This work is concerned with the development of a test emulation platform, termed as hand-in-hand test flow, of AMS circuits based on FPGA. The proposed methodology exploits fixed-point modeling and DSP implementation techniques facilitated by latest FPGAs to model the AMS circuits. The proposed hand-in-hand test flow for AMS circuits will help the test engineers to start their test plan concurrently with the design engineers and validate them much prior to the first silicon. We have illustrated the proposed scheme using the case study of a current programmed buck type switching converter on Xilinx® Virtex™-5 FPGA. The FPGA emulation measurement results show that performance of the emulated DC–DC buck converter (e.g., duty ratio test, line transient, load step) matches well with that of SPICE simulation.

A Design Technique for Embedded Electromagnetic Band Gap Structure in Load Board Applications

A new design technique and analysis for an embedded electromagnetic bandgap (EBG) structure is presented. In modern multifunction designs, it may be required to integrate noise-sensitive analog circuits next to digital circuits. Here, digital switching noise can propagate through power/ground planes and affect analog circuit performance. It is important to block this effect. To prevent the noise propagation, an EBG-patterned power/ground plane can be an acceptable solution. However, difficulties arise when the EBG structure is put in a stripline-like environment; the embedded EBG structure loses the noise filtering function. The reason for the functional failure is analyzed, followed by a solution. The proposed solution has been demonstrated by both simulation and measurement. Simulation and measurement results demonstrate that the proposed embedded EBG structure can be effective for the desired noise isolation. The design technique is tested on a prototype load board for a 10-bit 3-GHz analog-to-digital converter from National Semiconductor. The suggested design technique for the embedded EBG structure includes three design parameters: 1) the potentials of the planes above and below the EBG layer; 2) the thicknesses of the dielectric layers above and below the EBG layer; and 3) the number and position of vias interconnecting the top and bottom planes.

RF Load Board Tuning With 93K Feature

RF load boards are used as interface between DUT (device under test) and ATE tester. Its performance affects correlation with Bench and production yield rate directly. But issues from load board design and production can possibly involve problems. Performance usually is not as good as expected. For mass production different load boards from same design need show similar performance, the tolerance for them is very tight. That's why tuning for RF load board is so important. But tuning itself is not strict forward as school book, no accurate model for micro strip, lump components, and normally no accurate S parameters for DUT. It's time consuming and usually a procedure of trial by error. In this paper, transmission theory, Smith chart tool, which are useful for match circuits design are quickly reviewed. Then introduce how to design match circuits, which structure can be used, how many components are needed, what factors should be considered. Finally by demonstrating an example in real case, author tries to explain how to perform RF load board tuning with 93K ATE tester.

Improved IC Production Yield by Taking Into Account the Electromagnetic Interference Level During Testing

This paper presents a novel method for detecting test errors in radio frequency integrated circuit (RFIC) autotest-equipment (ATE) caused by electromagnetic interferences. A sensor for measuring ambient electromagnetic (EM) signals was used to determine whether interference was the cause of the reported testing error. Upon detecting a testing error, a retest procedure was actuated to recover the testing error and to improve yield loss. For theoretical validation, Monte Carlo procedure was applied in a “source-path-victim” model to simulate the effect of electromagnetic interference (EMI) on RFIC measurement. Finally, a four-element dual-band antenna array design printed onto an ATE load board is proposed. Both the numerical and measurement results validate the effectiveness of the proposed method in reducing testing errors caused by interference.

Test and Analysis of Friction Torque for Wind Turbine Pitch Bearing

In this paper, we introduce a new test method for friction performance of wind turbine pitch bearing. Four loading devices are used to put on load on the pitch bearing from different directions through load board. It can accurately simulate the axial force, radial force and overturning moment of wind turbine pitch bearing. The data acquisition device can measure the value of speed, torque and actual output load of loading hydraulic cylinder. After analysis and calculation, the influence of additional friction torque produced by loading device can be obviated, the friction torque of wind turbine pitch bearing under different loads can be test accurately in the laboratory. The research shows that the structure of test bed is compact, mechanical rigidity is good, the replacement of bearing model is expedient. It puts on load easily and can measure the frictional torque of wind turbine pitch bearing under different loads more accurately. It can provide data for performance analysis of wind turbine pitch bearing and ensure the pitch bearing satisfying the application requirements.

IMPEDANCE MATCHING CAPABILITY OF NOVEL SOCKET CONTACTOR DESIGN USING VARIABLE OPEN STUBFOR RF PACKAGING TESTING

In this paper, we will propose a new structure for a socket contactor applied to the lead-frame test board. This structure contains a variable open stub to match the impedance of the package and the load board. Its electrical property is considered superior to a conventional spring probe's, especially when it is applied to a QFP device. We will present its equivalent model and discuss this in detail. Note that the transmission line model we use is at this point a substitute for a physical structure. First, its RLC model will be constructed after we demonstrate its simulation and test data. Finally, we will use the MonteCarlo Method to analyze length inaccuracies in manufacturing and observe how this new structure works.

Signature Testing of Analog and RF Circuits: Algorithms and Methodology

There are mainly two factors responsible for rapidly escalating production test costs of today's RF and high-speed analog circuits: 1) the high cost of high-speed and RF automatic test equipments and 2) long test times required by elaborate performance tests. In this paper, we propose a low-cost test methodology for accelerated production testing of analog and RF integrated circuits. As opposed to prior work, the key contribution of this paper is a new test generation algorithm that directly tracks the ability of input test waveforms to predict the test specification values from the observed test response, even in the presence of measurement noise. The response of the device-under-test (DUT) is used as a signature from which all of the performance specifications are predicted. The applied test stimulus is optimized in such a way that the error between the measured DUT performances and the predicted DUT performances is minimized. While existing low-cost test approaches have only been applied to low- and medium-frequency analog circuits, the proposed methodology extends low-cost testing to RF integrated circuits by incorporating modulation of a baseband test stimulus and subsequent demodulation of the obtained response to obtain the DUT signature. The proposed low-cost solution can be easily built into a load board that can be interfaced to an inexpensive tester

Next Generation ADC Massive Parallel Testing with Real Time Parameter Evaluation

The paper describes the implementation of a novel Analog-to-Digital-Converter (ADC) test technique for next generation low cost massive parallel ADC testing using a Field Programmable Gate Array (FPGA) on tester load board. The goal is to test the ADC which is embedded in an automotive micro controller with only pure digital tester sources. Therefore, the analog test stimulus for the ADC is generated by using ??-modulation technique off-line and analog filtering on load board. The digital test response is analyzed by a FPGA in real time by comparing the measured data with a reference signal. The modular concept of FPGA evaluation allows for quick and flexible reaction on changing production test requirements. Simply by reprogramming the FPGA with a new module there is no need of any hardware reconfigurations. Measurements with a high precision reference ADC in laboratory environment show that the method is ready for production.

Low-Cost Test of Embedded RF/Analog/Mixed-Signal Circuits inSOPs

Increasing levels of integration and high speeds of operation have made the problem of testing complex systems-on-packages (SOPs) very difficult. Testing packages with multigigahertz RF and optical components is even more difficult as external tester costs tend to escalate rapidly beyond 3 GHz. The extent of the problem can be gauged by the fact that test cost is approaching almost 40% of the total manufacturing cost of these packages. To alleviate test costs, various solutions relying on built-off test (BOT) and built-in test (BIT) of embedded high-speed components of SOPs have been developed. These migrate some of the external tester functions to the tester load board (BOT) and to the package and the die encapsulated in the package (BIT) in an "intelligent" manner. This paper provides a discussion of the emerging BOT and BIT schemes for embedded high-speed RF/analog/mixed-signal circuits in SOPs. The pros and cons of each scheme are discussed and preliminary available data on case studies are presented.

Use of a field programmable gate array for education in manufacturing test and automatic test equipment

A novel approach to education in manufacturing test and automatic test equipment is described that makes use of a Xilinx XC4000 series field programmable gate array (FPGA). Automatic test equipment is first used to configure the chip as a desired circuit and then to apply test vectors to test the circuit for "manufacturing defects." The chip can be configured as either fault-free or faulty, and several different types of functional faults can be injected. Use of the programmable device enables education in use of automatic test equipment to be combined with education in generation of effective test vectors for fault detection and diagnosis and also enables different classes to use the same device and load board to represent different circuits. This approach is suitable for both academic and industrial environments and should be particularly useful for customer training by manufacturers of automatic test equipment.