Load Balanced Birkhoff-von Neumann Switches Research Articles

Multicast Load-Balanced Birkhoff-Von Neumann Switch With Greedy Scheduling

Internet traffic is still exhibiting an exponential growth. This exponential growth will certainly be continued given the Internet of Things (IoT) and Internet of Everything (IoE) predictions regarding the number of devices connected to the Internet in the near future. Also, many popular multicast services such as IPTV, distance learning, content distribution, distributive interactive gaming, collaborative computing and others are rapidly increasing amount of the Internet multicast traffic, thus, significantly contributing to the Internet traffic growth. The routers are typically designed to cope with unicast traffic. Multicast traffic can negatively impact performance of such routers and cause significant degradation of overall network performance. Hence, due to increasing importance and increasing amount of multicast traffic, there is a great need for a scalable switch architecture that efficiently forwards both unicast and multicast traffic. In this paper, we propose a novel scalable, efficient and frugal multicast switch architecture based on load balanced Birkhoff-von Neumann switch with greedy scheduling that achieves stable performance even at very high traffic loads. The proposed switch is compared to other popular multicast switch solutions. Comparison shows that our proposed multicast switch architecture outperforms other solutions in all tested common traffic scenarios at the most critical (highest) traffic loads.

Birkhoff-Von Neumann Switch Based on Greedy Scheduling

It is important to develop high performance packet switches that are highly scalable. Among the popular solutions are input queued (IQ) switches and load balanced Birkhoff-von Neumann (LB-BvN) switches. However, both solutions have their drawbacks. Switch configuration pattern in IQ switches is random which can limit the supported port speed. On the other hand, LB-BvN switches require two switching stages which increase the overall cost. Also, some LB-BvN solutions suffer from the packet out of sequence problem. In this paper, we propose a novel packet switch architecture that combines the best properties of the IQ and LB-BvN switches and eliminates their drawbacks.

Space‐memory‐memory Clos‐network switches with in‐sequence service

Clos-network switches have attracted a lot of attention because of their modularity and scalability. However, out-of-sequence problems weigh heavily against the application of buffered Clos-network switches. A space-memory-memory (SMM) Clos-network switch is proposed in this study which is able to provide in-sequence service. There are two features in the proposed switch which are different from the previously proposed schemes. First, two-stage load-balanced Birkhoff-von Neumann (LB-BvN) switches are adopted for each second-stage module. Second, no inter-stage matching is needed. The key idea to provide in-order cell delivery in the proposed SMM Clos-network switch is that cells belonging to the same flow will experience the identical delay when passing through the LB-BvN switches at the second stage, and arrive at their destined third-stage module in order. Each switching module operates independently, which makes the proposed SMM Clos-network switch practical to implement in hardware. Simulations show that the proposed switch can achieve high performance under both Bernoulli and Bursty arrival traffic.

Low Propagation Delay Load-Balanced 4$\,\times\,$4 Switch Fabric IC in 0.13-$\mu{\rm m}$ CMOS Technology

A load-balanced Birkhoff-von Neumann (LB-BvN) 4 × 4 switch fabric IC is proposed for feedback-based switch systems. This is fabricated in 0.13- μm CMOS technology and the chip area is 1.380 × 1.080 mm2. The overall data rate of the LB-BvN 4 × 4 switch fabric IC is up to 32 Gb/s (8 Gb/s/channel) with only 0.8 ns propagation delay. The LB-BvN switch is highly recommended for constructing the next-generation terabit switch. In a feedback-based switch system, the long propagation delay of the switch module reduces the system throughput significantly. In this paper, we present a scalable LB-BvN 4 × 4 switch fabric IC directly in the high-speed domain. By observing the deterministic switching pattern of the N×N LB-BvN switch, we present a low-complexity pattern generator that reduces the PG complexity from O(N3) to O(1). This technique reduces the propagation delay of the switch module from 30 to 0.8 ns, and also provides 80% area saving and 85% power saving compared to serializer-deserializer interfaces. The proposed LB-BvN 4 × 4 switch fabric IC is suitable for feedback-based switch systems to solve the throughput degradation problem.

Load-balanced differentiated services support switch

How to provide quality of service (QoS) guarantees in the routing and switching devices has become one of the key research topics in the areas of routing and switching technologies. Differentiated services architecture (DiffServ), which forwards packets based on their per-hop behaviours, is known as a promising way for supporting QoS in a high-speed backbone network scenario. Motivated by the load-balanced Birkhoff-von Neumann switch, which has received much attention recently because of its outstanding extensibility performance, in this study, the authors propose a new switch architecture called load-balanced DiffServ support switch (LBDS). LBDS consists of pipeline traffic bandwidth control, priority-based load balancing, and bandwidth-based priority scheduling to implement fast forwarding for expedited forwarding (EF) traffic and assured forwarding for AF classes of traffic. The authors evaluate LBDS by extensive theoretical analysis and comprehensive simulations. As expected, LBDS can provide bandwidth guarantees for both EF and AF traffic. We also show that under burst traffic arrivals, especially when the traffic arrival pattern is non-uniform and the load is above 0.6, LBDS performs much better delay performance than existing DiffServ support schemes.

Recursive Constructions of Parallel FIFO and LIFO Queues With Switched Delay Lines

One of the most popular approaches for the constructions of optical buffers needed for optical packet switching is to use switched delay lines (SDL). Recent advances in the literature have shown that there exist systematic SDL construction theories for various types of optical buffers, including first-in first-out (FIFO) multiplexers, FIFO queues, priority queues, linear compressors, nonovertaking delay lines, and flexible delay lines. As parallel FIFO queues with a shared buffer are widely used in many switch architectures, e.g., input-buffered switches and load-balanced Birkhoff-von Neumann switches, in this paper we propose a new SDL construction for such queues. The key idea of our construction for parallel FIFO queues with a shared buffer is two-level caching, where we construct a dual-port random request queue in the upper level (as a high switching speed storage device) and a system of scaled parallel FIFO queues with a shared buffer in the lower level (as a low switching speed storage device). By determining appropriate dumping thresholds and retrieving thresholds, we prove that the two-level cache can be operated as a system of parallel FIFO queues with a shared buffer. Moreover, such a two-level construction can be recursively expanded to an n-level construction, where we show that the number of 2times2 switches needed to construct a system of N parallel FIFO queues with a shared buffer B is O((NlogN)log(B/(NlogN))), for NGt1. For the case with N=1, i.e., a single FIFO queue with buffer B, the number of 2times2 switches needed is O(logB). This is of the same order as that previously obtained by Chang We also show that our two-level recursive construction can be extended to construct a system of N parallel last-in first-out (LIFO) queues with a shared buffer by using the same number of 2times2 switches, i.e., O((NlogN)log(B/(NlogN))), for NGt1 and O(logB) for N=1. Finally, we show that a great advantage of our construction is its fault tolerant capability. The reliability of our construction can be increased by simply adding extra optical memory cells (the basic elements in our construction) in each level so that our construction still works even when some of the optical memory cells do not function properly

Decoupled parallel hierarchical matching schedulers

AbstractThe load balanced Birkhoff–von Neumann switch is an elegant VOQ architecture with two outstanding characteristics: (i) it has a computational cost of O(1) iterations and (ii) input controllers do not exchange information (as a result, it allows decoupled implementations with a low power density). The load balancing stage guarantees stability under a broad class of traffic patterns. It may alter packet sequence, but this can be solved with appropriate packet selection strategies.The average packet delay caused by previous maximal size matching algorithms, such as iSLIP, RDSRR, or PHM is noticeably lower than that of a Birkhoff–von Neumann switch, especially for low and medium loads. However, they need tightly coupled VOQ controllers, which implies higher power density. For example, this makes difficult to apply those algorithms to optical switching architectures. Moreover, they require O(log2 N) iterations to converge, and this computational cost may be unacceptable for the slot lengths in optical packet switches.In this paper, we propose a family of decoupled Parallel Hierarchical Matching (PHM) VOQ controllers (DPHM). They outperform the Birkhoff–von Neumann scheduler, which can be viewed as a member of the family (in fact, the simplest one). DPHM schedulers have a computational cost of O(1) iterations and, unlike last generation maximal size matching algorithms, they allow a low input controller interconnection complexity (low power density switch implementation). Copyright © 2006 John Wiley & Sons, Ltd.

Providing guaranteed rate services in the load balanced Birkhoff-von Neumann switches

In this paper, we propose two schemes for the load balanced Birkhoff-von Neumann switches to provide guaranteed rate services. The first scheme is based on an earliest eligible time first (EETF) policy. In such a scheme, we assign every packet of a guaranteed rate flow a targeted departure time that is the departure time from the corresponding work conserving link with capacity equal to the guaranteed rate. By implementing the EETF policy with jitter control mechanisms and first come first serve (FCFS) queues, we show that the end-to-end delay for every packet of a guaranteed rate flow is bounded by the sum of its targeted departure time and a constant that only depends on the number of flows and the size of the switch.Our second scheme is a frame based scheme as in Keslassy and McKeown, 2002. There, time slots are grouped into fixed size frames. Packets are placed in appropriate bins (buffers) according to their arrival times and their flows. We show that if the incoming traffic satisfies certain rate assumptions, then the end-to-end delay for every packet and the size of the central buffers are both bounded by constants that only depend on the size of the switches and the frame size. The second scheme is much simpler than the first one in many aspects: 1) the on-line complexity is O(1) as there is no need for complicated scheduling; 2) central buffers are finite and thus can be built into a single chip; 3) connection patterns of the two switch fabrics are changed less frequently; 4) there is no need for resequencing-and-output buffer after the second stage; and 5) variable length packets may be handled without segmentation and reassembly.

Load balanced Birkhoff-von Neumann switches with resequencing

Load balanced Birkhoff-von Neumann switches with resequencing

Load balanced Birkhoff–von Neumann switches, part I: one-stage buffering

Motivated by the need for a simple and high performance switch architecture that scales up with the speed of fiber optics, we propose a switch architecture with two-stage switching fabrics and one-stage buffering. The first stage performs load balancing, while the second stage is a Birkhoff–von Neumann input-buffered switch that performs switching for load balanced traffic. Such a switch is called the load balanced Birkhoff–von Neumann switch in this paper. The on-line complexity of the switch is O(1). It is shown that under a mild technical condition on the input traffic, the load balanced Birkhoff–von Neumann switch achieves 100% throughput as an output-buffered switch for both unicast and multicast traffic with fan-out splitting. When input traffic is bursty, we show that load balancing is very effective in reducing delay, and the average delay of the load balanced Birkhoff–von Neumann switch is proven to converge to that of an output-buffered switch under heavy load. Also, by simulations, we demonstrate that load balancing is more effective than the conflict resolution algorithm, i-SLIP, in heavy load. When both the load balanced Birkhoff–von Neumann switch and the corresponding output-buffered switch are allocated with the same finite amount of buffer at each port, we also show that the packet loss probability in the load balanced Birkhoff–von Neumann switch is much smaller than that in an output-buffered switch, when the buffer is large.

Load balanced Birkhoff–von Neumann switches, part II: multi-stage buffering

The main objective of this sequel is to solve the out-of-sequence problem that occurs in the load balanced Birkhoff–von Neumann switch with one-stage buffering. We do this by adding a load-balancing buffer in front of the first stage and a resequencing-and-output buffer after the second stage. Moreover, packets are distributed at the first stage according to their flows, instead of their arrival times in part I. In this paper, we consider multicasting flows with two types of scheduling policies: the first come first served (FCFS) policy and the earliest deadline first (EDF) policy. The FCFS policy requires a jitter control mechanism in front of the second stage to ensure proper ordering of the traffic entering the second stage. For the EDF scheme, there is no need for jitter control. It uses the departure times of the corresponding FCFS output-buffered switch as deadlines and schedules packets according to their deadlines. For both policies, we show that the end-to-end delay through our multi-stage switch is bounded above by the sum of the delay from the corresponding FCFS output-buffered switch and a constant that only depends on the size of the switch and the number of multicasting flows supported by the switch.