LO Feedthrough Research Articles

A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression

A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression

A D-Band Wideband Single-Ended Neutralized Upconversion Mixer With Controlled LO Feedthrough in 65-nm CMOS

A D-Band Wideband Single-Ended Neutralized Upconversion Mixer With Controlled LO Feedthrough in 65-nm CMOS

248 GHz Sub-Harmonic Mixer Last Transmitter With I/Q Imbalance and LO Feedthrough Calibration

248 GHz Sub-Harmonic Mixer Last Transmitter With I/Q Imbalance and LO Feedthrough Calibration

Wideband 120-GHz CMOS I/Q Transmitter With Suppressed IMRR and LOFT for Wireless Short-Range High-Speed 6G IoT Applications

In this study, a wideband 120-GHz I/Q transmitter with suppressed image rejection ratio (IMRR) and LO feedthrough (LOFT) is presented using 40-nm complementary metal oxide semiconductor technology. For the up-conversion mixer, an NMOS/PMOS pair with resistive feedback is used during the transconductance stage to increase the input bandwidth with gain boosting, and a novel switching core without LO-RF coupling is used to suppress the LOFT effect. For the quadrature injection locked tripler, an I/Q calibration circuit is inserted to minimize the I/Q mismatch; accordingly, the measured IMRR is greatly improved. The peak conversion gain of the proposed transmitter was 10.8 dB, and the 3-dB gain bandwidth was 20 GHz. The measured IMD2 and IMD3 were above 40 dBc. Moreover, the IMRR was measured as 43.1 dBc, applying I/Q calibration. The measured LOFT was 33.7 dBc. The data rate of the proposed transmitter was measured up to 20 Gbps and at a distance of 5 cm. Subsequently, the error vector magnitudes were 13.4 dB for QPSK and -19.1 dB for 16-QAM modulation. It is expected that such wireless high-speed communication can be applied to wireless short range high-speed 6G IoT applications.

28-GHz CMOS Direct-Conversion RF Transmitter with Precise and Wide-Range Mismatch Calibration Techniques

A millimeter-wave direct-conversion radio-frequency (RF) transmitter requires precise in-/quadrature-phase (I/Q) mismatch calibration and dc offset cancellation to minimize image rejection ratio (IRR) and LO feedthrough (LOFT) for ensuring satisfactory output spectral purity. We present a 28-GHz CMOS RF transmitter with an improved calibration technique for fifth generation (5G) wireless communication applications. The RF transmitter comprises a baseband amplifier, quadrature up-conversion mixer, power amplifier driver, and quadrature LO generator. The I/Q amplitude mismatch is calibrated by tuning the gate biases of the switching stage FETs of the mixer, the I/Q phase mismatch is calibrated by tuning the varactor capacitances at the LC load of LO buffer, and the dc offset is cancelled by tuning the body voltages of the differential-pair FETs at the baseband amplifier. The proposed technique provides precise calibration accuracy by employing mV-resolution tuning voltage generation via 6-bit voltage digital-to-analog converters. It also covers wide calibration range while minimizing the impact on the circuit’s bias point and dissipated current during calibration. Implemented in a 65 nm CMOS process, the RF transmitter integrated circuit shows output-referred 1 dB compression power of +6.5 dBm, saturated output power of +12.6 dBm, and an operating band of 27.5–29.3 GHz while demonstrating satisfactory performances of −55.9 dBc of IRR and −36.8 dBc of LOFT.

A Millimeter-Wave Mutual-Coupling-Resilient Double-Quadrature Transmitter for 5G Applications

This article presents a wideband energy-efficient transmitter (TX) for 5G mm-wave phased-array systems. It features an advanced double-quadrature direct upconverter (DQ-DUC) to improve its in-band linearity and spectral purity. The proposed TX architecture incorporates an efficiency-enhanced balanced power amplifier (EEBPA) that mitigates VSWR fluctuations in phased-array systems while enhancing efficiency at power back-off (PBO). The EEBPA comprises two identical series-Doherty power amplifiers (PAs) combined through a quadrature hybrid coupler forming a balanced PA. The proposed DQ-DUC consists of a pair of I/Q modulators and the proposed EEBPA’s quadrature combiner to further suppress the I/Q image. To verify the proposed techniques, a 40-nm CMOS prototype is implemented. It delivers 20 dBm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P~_{\text {1 dB}}$ </tex-math></inline-formula> with 40%/31% drain efficiency at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P~_{\text {1 dB}}$ </tex-math></inline-formula> /6-dB PBO. The measured TX output reflection coefficient is better than −18 dB over a 22.5–30-GHz band. Its intrinsic LO feedthrough and image-rejection ratio for a 100-MHz tone spacing over a 24–30-GHz band are better than −45 dBc/50 dB, respectively, without calibration. The average error vector magnitude (EVM) is better than −27.1 dB without digital pre-distortion for an eight-carrier “100-MHz 64-QAM OFDM” signal with an 800-MHz aggregated bandwidth while generating an average output power of 8.4 dBm with 10.8% drain efficiency. Its maximum forward-power/EVM deviations are better than 0.3/1.65 dB, respectively, for a “100-MHz 64-QAM” signal under a voltage standing wave ratio of 3.

System Performance of a Scalable 79 GHz Imaging MIMO Radar With Injection-Locked LO Feedthrough

The estimation of the direction-of-arrival in a coherent multi-channel radar system requires the distribution of the high-frequency local oscillator signal to all hardware channels. Various system concepts with distribution network or feedthrough topologies are established. While distribution networks are bulky and costly, the time delays in systems with a feedthrough topology cause systematic errors in the range evaluation. In this work, a system concept based on an injection-locked feedthrough and the related radar system analysis is presented. The disadvantage of time delays in common feedthrough architectures can be eliminated by a hardware correction using the phase shifting capabilities of the injection-locked oscillator. In addition, two software correction algorithms are presented and analyzed. The performance of the realized system is shown by radar measurements and direction-of-arrival estimations. It is proven that the phase noise of different injection-locked oscillators is fully correlated within the radar system which results in the same detection performance as in state-of-the-art radar systems using a signal distribution network. Thus, the injection-locked feedthrough imaging radar topology is a suitable concept of realizing flexible radar frontends without bulky distribution networks.

A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS

This article presents the first 39-GHz phased-array transceiver (TRX) chipset for fifth-generation new radio (5G NR). The proposed transceiver chipset consists of 4 sub-array TRX elements with local-oscillator (LO) phase-shifting architecture and built-in calibration on phase and amplitude. The calibration scheme is proposed to alleviate phase and amplitude mismatch between each sub-array TRX element, especially for a large-array transceiver system in the base station (BS). Based on LO phase-shifting architecture, the transceiver has a 0.04-dB maximum gain variation over the 360° full tuning range, allowing constant-gain characteristic during phase calibration. A phase-to-digital converter (PDC) and a high-resolution phase-detection mechanism are proposed for highly accurate phase calibration. The built-in calibration has a measured accuracy of 0.08° rms phase error and 0.01-dB rms amplitude error. Moreover, a pseudo-single-balanced mixer is proposed for LO-feedthrough (LOFT) cancellation and sub-array TRX LO-to-LO isolation. The transceiver is fabricated in standard 65-nm CMOS technology with flip-chip packaging. The 8TX-8RX phased-array transceiver module 1-m OTA measurement supports 5G NR 400-MHz 256-QAM OFDMA modulation with -30.0-dB EVM. The 64-element transceiver has a EIRPMAX of 53 dBm. The four-element chip consumes a power of 1.5 W in the TX mode and 0.5 W in the RX mode.

An ISM Band High-Linear Current-Reuse Up-Conversion Mixer With Built-in-Self-Calibration for LOFT and I/Q Imbalance

This brief presents a high-linear current-reuse upconversion mixer with built-in-self-calibration for LO feed through (LOFT) and I/Q imbalance for the 2.4GHz ISM band transmitter. Exploiting the negative feedback loop and the saturated switches biased by the current bleeding, third-order intermodulation (IM3) products are eliminated. Based on the fully differential push-pull OP-AMP and current mirror, the current-reuse input transconductance with a boosted gain is achieved. LOFT and I/Q imbalance calibrations are carried out utilizing two fully-integrated auto-calibration loops with the auto-zero comparator and the low noise envelope detector, respectively. Fabricated in 40 nm LP CMOS technology, the mixer shows 15.02 dBm OIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and -1.80 dBm OP1dB while consuming 12.75 mW from 1.1 V power supply for 4.17 dB gain. Along with the third-order filter, the up-conversion mixer achieves >40 dBc LO suppression ration (LSR) and 50.6 dBc image rejection ration (IMRR) within ±2 dB deviation among 10 MHz bandwidth, thanks to the two calibration loops.

A folded-cascode mixer for mixing-spur suppressions in a 2.4-to-5.8 GHz transmitter

This paper presents a folded-cascode mixer for an ISM band transmitter that translates the signals at the 2.4 GHz band to 5.8 GHz. Comparing to the conventional Gilbert cell mixer, our proposed folded-cascode mixer architecture with DC offset blocking, and transconductance linearization techniques can effectively suppress the LO feedthrough by 9 dB. The proposed mixer is designed in 0.11 μm CMOS and consumes 2.6 mA from a 1.2 V supply. The simulation results show that the mixer achieves an output power of 4.7 dBm, and all the emission spurs are well below −40dBc.

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance

This paper presents a 60-GHz CMOS transceiver targeting the IEEE 802.11ay standard. A calibration block for local oscillator feedthrough (LOFT) and I/Q imbalance featuring high accuracy and low power consumption is integrated with the transceiver. With the help of the proposed calibration, this paper is capable of boosting the data rate with higher order modulation scheme and wider channel-bonding bandwidth, which are demanded by IEEE 802.11ay. At the same time, it maintains the compatibility with the existing IEEE 802.11ad standard. This paper reports a two-channel-bonding data rate of 24.64 Gb/s in 128 quadrature amplitude modulation (QAM). The corresponding TX-to-RX error vector magnitude (EVM) is −26.1 dB. Furthermore, a four-channel-bonding data rate of 42.24 Gb/s in 64 QAM is realized with a single-element transceiver. The measured maximum data rate is 50.1 Gb/s in 64 QAM, which is the highest data rate achieved in the 60-GHz band. The power consumption is only 169 mW in the transmitting mode and 139 mW in the receiving mode.

A 40 nm CMOS E-Band Transmitter With Compact and Symmetrical Layout Floor-Plans

This paper describes a direct-conversion E-band transmitter (TX) in 40 nm bulk CMOS. As millimeter-wave (mm-Wave) circuits are vulnerable to process variations including the mismatch between interconnects, this E-band TX design is conducted in a layout floor-plan oriented way. Compact and symmetrical floor-plans of poly-phase filter (PPF) and I/Q modulator are presented in this work to suppress the LO feed-through (LOFT) and I/Q imbalance over both 71–76 and 81–86 GHz bands. In addition, a systematic design methodology is proposed for the mm-Wave PPF to reduce required EM simulations. The calibration methods used in this design are easy to implement for further reducing LOFT and I/Q imbalance with negligible impact on other TX performance metrics. The 0.225 mm $^{2}$ E-band TX achieves a measured output power of 12 dBm and efficiency of 15% with about 15 GHz bandwidth. It features an uncalibrated I/Q imbalance of less than 30 dB from 62.5 to 85.5 GHz. The calibration circuits further reduce the I/Q imbalance by about 4 dB and ensure the LOFT of less than $-$ 30 dBc over more than 30 dB output dynamic range. The presented TX achieves 4.5 Gb/s 64-QAM and 14 Gb/s 16-QAM.

A Low-Power WCDMA Transmitter With an Integrated Notch Filter

A filtering technique to attenuate the receive-band noise enables a 65-nm CMOS WCDMA transmitter to achieve an output noise level of -160 dBc/Hz at 80-MHz offset, while dissipating 65 mW. Using a feedback filtering technique, the circuit introduces a null with an arbitrary width at the receive frequency and eliminates the need for an external SAW filter. A stability analysis is performed to choose the most suitable architecture for the feedback path, which ensures stability over a wide range of loop-gain. Nonideal effects such as quadrature phase and gain errors, LO feedthrough, harmonic downconversion and phase-noise are also analyzed.

A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters

A wideband software-defined digital-RF modulator targeting Gb/s data rates is presented. The modulator consists of a 2.625-GS/s digital DeltaSigma modulator, a 5.25-GHz direct digital-RF converter, and a fourth-order auto-tuned passive LC RF bandpass filter. The architecture removes high dynamic range analog circuits from the baseband signal path, replacing them with high-speed digital circuits to take advantage of digital CMOS scaling. The integration of the digital-RF converter with an RF bandpass reconstruction filter eliminates spurious signals and noise associated with direct digital-RF conversion. An efficient passgate adder circuit lowers the power consumption of the high-speed digital processing and a quadrature digital-IF approach is employed to reduce LO feedthrough and image spurs. The digital-RF modulator is software programmable to support variable bandwidths, adaptive modulation schemes, and multi-channel operation within a frequency band. A prototype IC built in 0.13-mum CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. In-band LO and image spurs are less than -59 dBc without requiring calibration. The modulator consumes 187 mW and occupies a die area of 0.72 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 0.18 μm CMOS single‐balanced mixer with LO cancellation for MB‐OFDM UWB direct conversion receiver applications

AbstractThis article presents an effective methodology for designing a CMOS single‐balanced down conversion mixer with LO cancellation for MB‐OFDM UWB direct‐conversion receiver. The most crucial drawback of single‐balanced mixer; LO feedthrough is overcome by employing BPF technique for multi‐channel LO signal. The proposed single‐balanced mixer is implemented with 0.18 μm CMOS technology and it operates from 3 to 5 GHz frequency range. The measurement result shows that LO signal amplitude is less than IF signal, the IIP3 is 1 dBm at 4‐GHz band, and the current consumption is 6 mA. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 2555–2558, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22793

A 2-GS/s 3-bit /spl Delta//spl Sigma/-modulated DAC with tunable bandpass mismatch shaping

Direct digital synthesis of signals in the hundreds of megahertz can lead to simpler, smaller transceivers, free of images and LO feedthrough that plague systems requiring analog upconversion. We present a 3-bit, 2 GS/s, /spl Delta//spl Sigma/-modulated DAC in InP HBT technology. The DAC is linearized using bandpass mismatch shaping. The mismatch shaper uses seven tunable 1.5-bit discrete-time bandpass /spl Delta//spl Sigma/ modulators to dynamically route the digital signals to the DACs. These /spl Delta//spl Sigma/ modulators operate in the analog domain to decrease system complexity and power consumption. The mismatch-shaped DAC can generate narrowband signals between 250-750 MHz with >68 dB SNR in a 1-MHz bw, >74-dB SFDR, and <-80-dBc intermodulation distortion with an 8.1-W power consumption.