Lithography Technology Research Articles

Bandwidth-aware fast inverse lithography technology using Nesterov accelerated gradient

Inverse lithography technology (ILT) is a leading-edge method for improving the resolution and image fidelity of optical lithography systems in semiconductor manufacturing. However, the massive computational complexity of ILT presents the inherent runtime bottleneck, which hinders its application to the large-scale lithography layouts. This paper innovates a fast ILT method by reducing both of the inherent algorithmic complexity and the required iteration number. Based on the diffraction-limited nature of optical lithography system, a bandwidth-aware acceleration approach is applied to reduce the calculation complexities of the forward imaging model and inverse gradient computation in each ILT iteration. In addition, a carefully designed algorithm based on the Nesterov accelerated gradient (NAG) is developed to achieve nearly quadratic convergence rate, thereby reducing the total number of iterations required to obtain the optimal solution. Numerical experiments show that the proposed method can improve the speed by hundreds of times over the traditional gradient-based ILT algorithms without sacrificing accuracy.

Dynamic photomask directed lithography based on electrically stimulated nematic liquid crystal architectures

Lithography technology is a powerful tool for preparing complex microstructures through projecting patterns from static templates with permanent features onto samples. To simplify fabrication and alignment processes, dynamic photomask for multiple configurations preparation becomes increasingly noteworthy. Hereby, we report a dynamic photomask by assembling the electrically stimulated nematic liquid crystal (NLC) into multifarious architectures. This results in reconfigurable and switchable diffraction patterns due to the hybrid phase arising from the NLC molecular orientations. These diffraction patterns are adopted as metamask to produce multiple microstructures with height gradients in one-step exposure and hierarchical microstructures through multiple in-situ exposures using standard photolithography. The fabricated pattern has feature size about 3.2 times smaller than the electrode pattern and can be transferred onto silicon wafer. This strategy can be extended to design diverse microstructures with great flexibility and controllability, offers a promising avenue for fabricating metamaterials via complex structures with simplified lithography processes.

Research on Chip Manufacturing and Fault Detection Technology

In the wave of the digital era, the chip plays a key role in promoting the whole information technology revolution with its core position in the development of world science and technology. As the cornerstone of computing and data processing, the development of chips has promoted the progress of the entire technology field. The chip’s manufacturing is the key to determining the performance and computing power of the whole chip, and fault detection technology in the production process is an important part of determining the product’s quality and cost. Therefore, under the background of Moore’s law approaching the physical limit, how to ensure the yield of chip production while continuing to improve chip performance has become a major challenge for the chip manufacturing industry. Based on this, this paper summarizes the key manufacturing steps of the chip. The chip manufacturing technology is comprehensively sorted from design to silicon wafer manufacturing, photolithography, etching, ion implantation, and other processes. At the same time, the research direction of monocrystalline silicon manufacturing technology and the existing lithography technology are introduced, including optical lithography, extreme ultraviolet lithography, electron beam lithography, and so on. Fault detection technology in chip production has also been introduced. In addition, the chip manufacturing and fault detection technology introduced in this paper is summarized and its future development is prospected, which provides reference and inspiration for promoting the continuous progress of chip technology.

Kill Two Birds with One Stone: Cracking Lithography Technology for High-Performance Flexible Metallic Network Transparent Conductors and Metallic Micronano Sheets.

Flexible electronics have sparked a wide range of exciting applications, such as flexible display technologies, lighting, sensing, etc. Flexible conductors are essential components of flexible electronics and seriously affect efficiency and overall performance. Here, a facile and kill-two-birds-with-one-stone strategy of cracking lithography technology has been proposed to simultaneously fabricate two high-performance flexible conductors, flexible metallic network transparent conductors (f-NTCs) and metallic micronano sheets (MMNSs). The PET substrate flexible transparent conductors (FTCs) based on this strategy yield 88.1% transparency within the visible spectrum and a sheet resistance of 9 Ω/sq. In addition, the FTCs show exceptional mechanical stability, with the sheet resistance remaining virtually unchanged even after 6000 s of bending tests. Subsequently, the remaining MMNSs are recycled to manufacture a Ag paste, showing a very low conductive percolation threshold (∼13%) and excellent flexibility with 140% breaking elongation. After 1000 s of stretching tests, it showed excellent mechanical stability. Furthermore, flexible electroluminescent devices based on the FTCs and sensors fabricated with MMNSs both show excellent performance, demonstrating their potential wide applications in flexible electronics.

Plasmonic image reproduction with solid-state superionic stamping (S4)

Traditional top-down approaches for producing metallic nanostructures, despite being capable of producing arbitrary 2-D shapes, often use vacuum-based deep sub-micron lithographic fabrication technologies. This makes their use for single-use devices like chemical and bio-sensing substrates difficult to economically justify. Here, the authors demonstrate a manufacturing pathway that only uses such techniques to produce a master. This reusable master, coupled with a unique and facile electrochemical imprinting process, Solid-State Superionic Stamping (S4), is used to produce several replicated metallic nanostructures, thus demonstrating an economically feasible manufacturing pathway for single-use, nano-enabled devices.This paper uses plasmonic image reproduction as an easy-to-visualize proxy for single-use devices such as plasmonic sensors and Surface Enhanced Raman Spectroscopy (SERS) substrates that require nanopatterned metallic structures. It demonstrates a process for replicating a picture by a set of metallic structures that plasmonically produce the desired colors locally. It uses a digitizing computational tool, direct-write Two-Photon Lithography (TPL) and a dry-etch process to rapidly produce a silicon master. This master is used to hot emboss nano-patterns in superionic glass blanks that, in turn, are used for electrochemical imprinting with S4 to reproduce the patterns on Ag substrates. The different steps in this process flow are described along with their role and effectiveness in contributing to a high-fidelity plasmonic image reproduction.

E-beam Lithography Technology for Quantum Device Fabrication and Nanoscale Patterning

Currently nanotechnology becoming more important with the implementation of nano devices including quantum devices. In this paper, we will briefly introduce the JEOL JBX-8100FS e-beam lithography tool which was recently installed in Hallym University and the current status of the exposure conditions set up. As applications using e-beam lithography tool, we will introduce Schottky barrier single hole transistor and silicon nanowire thermoelectric device, respectively. We are under researching plasmonic and quantum devices as basic research.

Nondestructive Demolding of Structure-Designable High-Aspect-Ratio Nanoimprint Template.

Demolding is a crucial step in nanoimprint lithography (NIL) for successfully transferring template structures onto resist materials. The process, however, is often hindered by the adhesion and friction between the template and resist, leading to inevitable defects on the replicas and posing challenges in replicating templates with high-aspect-ratio (HAR) structures. Here, we introduce a novel approach using the dissolvable template method to achieve the nondestructive demolding of structure-designable HAR nanoimprint templates. The templates were fabricated by the 3D lithography technology, employing a positive photoresist that can be easily dissolved in alkaline solutions after exposure to ultraviolet (UV) radiation. By implementing this method, we successfully transferred dense arrays of pillars with a minimal diameter of 1.2 μm and a significant aspect ratio of 18, as well as a microlens array diffuser with randomly distributed structural parameters. The dissolvable template method paves the way for stress-free demolding, broadening NIL's application range.

Shortened and simplified traceability chain for dimensional metrology based on self-traceable standards

Abstract Nanoscale measurement is an essential task of nanomanufacturing, and measurement traceability is a fundamental aspect of nanoscale measurement. High-precision nanoscale measurement instruments (e.g. atomic force microscopes (AFM) and scanning electron microscopes (SEM)) need to be calibrated by traceable standards to ensure their accuracy and reliability. However, due to the suboptimal accuracy, uniformity, and consistency of existing standards, they need to be calibrated by metrological instruments traceable to primary length standards (e.g. physical wavelength standards) before use. This results in a long traceability chain that leads to error accumulation and significantly reduces calibration efficiency. This paper proposes a novel shortened and simplified traceability chain, where the physical wavelength standard corresponding to the 7S3 → 7P4° transition frequency of chromium atoms is materialized into self-traceable gratings using the atom lithography technology. The self-traceable gratings can then be directly applied for calibrating measurement instruments. To verify this approach, the self-traceable gratings are calibrated using a metrological AFM of the Physikalisch-Technische Bundesanstalt. Measurement results confirmed the feasibility of the approach. Particularly, our results show that the self-traceable gratings have excellent uniformity over different measurement areas and consistency over different samples, both at 0.001 nm level. Finally, the application of the self-traceable gratings for the calibrations of a commercial AFM and SEM is demonstrated. The new traceability chain significantly simplifies the calibration process, providing a more reliable and higher efficient calibration approach for advanced nanomanufacturing than that of the state-of-the-art.

Comparative Analysis of Positive Photoresist and Negative Photoresist in Nanoimprint Lithography Technology

Comparative Analysis of Positive Photoresist and Negative Photoresist in Nanoimprint Lithography Technology

Probing Nanotopography-Mediated Macrophage Polarization via Integrated Machine Learning and Combinatorial Biophysical Cue Mapping.

Inflammatory responses, leading to fibrosis and potential host rejection, significantly hinder the long-term success and widespread adoption of biomedical implants. The ability to control and investigated macrophage inflammatory responses at the implant-macrophage interface would be critical for reducing chronic inflammation and improving tissue integration. Nonetheless, the systematic investigation of how surface topography affects macrophage polarization is typically complicated by the restricted complexity of accessible nanostructures, difficulties in achieving exact control, and biased preselection of experimental parameters. In response to these problems, we developed a large-scale, high-content combinatorial biophysical cue (CBC) array for enabling high-throughput screening (HTS) of the effects of nanotopography on macrophage polarization and subsequent inflammatory processes. Our CBC array, created utilizing the dynamic laser interference lithography (DLIL) technology, contains over 1 million nanotopographies, ranging from nanolines and nanogrids to intricate hierarchical structures with dimensions ranging from 100 nm to several microns. Using machine learning (ML) based on the Gaussian process regression algorithm, we successfully identified certain topographical signals that either repress (pro-M2) or stimulate (pro-M1) macrophage polarization. The upscaling of these nanotopographies for further examination has shown mechanisms such as cytoskeletal remodeling and ROCK-dependent epigenetic activation to be critical to the mechanotransduction pathways regulating macrophage fate. Thus, we have also developed a platform combining advanced DLIL nanofabrication techniques, HTS, ML-driven prediction of nanobio interactions, and mechanotransduction pathway evaluation. In short, our developed platform technology not only improves our ability to investigate and understand nanotopography-regulated macrophage inflammatory responses but also holds great potential for guiding the design of nanostructured coatings for therapeutic biomaterials and biomedical implants.

Robust van der Waals Metal Mask for Residue‐Free and All‐Solid 2D Material Engineering

AbstractThe van der Waals (vdW) contact, characterized by its bondless interactions, opens up exciting possibilities in cutting‐edge mask technology. It enables incredibly close proximity to samples at the atomic level while facilitating non‐destructive engineering. In this study, the concept of a vdW metal mask using the template striped ultra‐flat Ag/Au film is introduced. The probe tip‐assisted metal film transfer under an optical microscope is employed to showcase all‐solid and residue‐free engineering on 2D materials. The robust nature of the vdW metal mask allows for various treatments, including gas, liquid, solid, plasma, and light, making it a universal tool for fabricating 2D material‐based devices and samples with sub‐1 µm resolution, all without the need for lithography technologies. With the superiority in simple sample fabrication, ultra‐clean surfaces, and robustness under harsh conditions, the technique is believed to flourish in the 2D material research field.

Mask optimization for optical lithography based on UNet

Abstract Traditional photolithography methods are increasingly unable to meet the ever-stringent demands for pattern resolution and alignment accuracy, and developing efficient mask optimization techniques has become an urgent need in the industry. This paper delves into the application of Inverse Lithography Technology (ILT) in nanoscale photolithography and proposes an improved mask optimization algorithm. The backbone network of this algorithm employs a UNet architecture, trained initially on a prepared dataset comprising original masks and the ones optimized through traditional methods. The pre-trained backbone network generates a coarse mask, which is then inputted into a correction layer to refine the mask, enhancing pattern accuracy and processing efficiency. Compared to traditional gradient-based mask optimization methods, neural ILT demonstrates superior effectiveness, which enhances the efficiency and pattern quality of the lithography process while reducing production costs.

A Novel Device for Micro-Droplets Generation Based on the Stepwise Membrane Emulsification Principle.

This paper presents a novel design of the device to generate microspheres or micro-droplets based on the membrane emulsification principle. Specifically, the novelty of the device lies in a proposed two-layer or stepwise (by generalization) membrane structure. An important benefit of the stepwise membrane is that it can be fabricated with the low-cost material (SU-8) and using the conventional lithography technology along with a conventional image-based alignment technique. The experiment to examine the effectiveness of the proposed membrane was conducted, and the result shows that microspheres with the size of 2.3 μm and with the size uniformity of 0.8 μm can be achieved, which meets the requirements for most applications in industries. It is noted that the traditional membrane emulsification method can only produce microspheres of around 20 μm. The main contribution of this paper is thus the new design principle of membranes (i.e., stepwise structure), which can be made by the cost-effective fabrication technique, for high performance of droplets production.

Photonic topological phase transition induced by material phase transition.

Photonic topological insulators (PTIs) have been proposed as an analogy to topological insulators in electronic systems. In particular, two-dimensional PTIs have gained attention for the integrated circuit applications. However, controlling the topological phase after fabrication is difficult because the photonic topology requires the built-in specific structures. This study experimentally demonstrates the band inversion in two-dimensional PTI induced by the phase transition of deliberately designed nanopatterns of a phase change material, Ge2Sb2Te5 (GST), which indicates the first observation of the photonic topological phase transition in two-dimensional PTI with changes in the Chern number. This approach allows us to directly alter the topological invariants, which is achieved by symmetry-breaking perturbation through GST nanopatterns with different symmetry from original PTI. The success of our scheme is attributed to the ultrafine lithographic alignment technologies of GST nanopatterns. These results demonstrate how to control photonic topological properties in a reconfigurable manner, providing insight into the possibilities for reconfigurable photonic processing circuits.

Improving the working distance for near-field lithography with supercell photonic crystal

Near-field lithography technology plays a vital role in chip manufacturing. However, near-field lithography devices with acceptable working distance (WD) have become a long-term pursuit for researchers. Here, a one-dimensional supercell photonic crystal (SPC) is proposed for near-field lithography. The simulation results show that the PCs could provide an air WD of over 100 nm in interference lithography and produce patterns with a resolution reach ∼67 nm (∼λ/6). The analyses indicate that using SPCs in interference lithography can make it more suitable for practical manufacturing. Furthermore, this type of PC can also be used in direct writing lithography. The simulation results show that the direct writing lithography could be realized with a WD of 100 nm, and the full width at half maximum of the focal spot is ∼137 nm. The principle presents a new method for controlling the evanescent waves, and the method would greatly promote the development and application of near field lithography.

High throughput observation of latent images on resist using laser-based photoemission electron microscopy

The rapid evolution of lithography technology necessitates faster pattern inspection methods. Here, we propose the use of laser-based photoemission electron microscopy (laser-PEEM) for high-throughput observation of latent images on an electron beam resist. We revealed that this technique can visualize latent images as chemical contrasts, and estimated the throughput millions of times higher than those of an atomic force microscope. Moreover, we estimated that throughput tens of thousands of times higher than a single-beam scanning electron microscope is achievable for post-developed resist patterns. This breakthrough highlights the potential of laser-PEEM to revolutionize a high-throughput lithographic pattern inspection in semiconductor manufacturing.

The evolution of silicon integrated circuit technologyfrom scaling to lower power consumption

With the rapid development of silicon-based microelectronics industry, the silicon-based microelectronics industry are reaching a point where microelectronics can no longer simply scaled to increasingly small sizes, and power consumption controlling are becoming increasingly important. The article starts from the early development of silicon integrated circuit and addresses how the focus transferred from scaling to scaling to lower power consumption. Based on that, the article makes a systematic review of all the technologies of contributing to lower power consumption, from designing to manufacturing, from architecture to circuit level. The article also introduces new devices and architectures adapting 3D integrated circuit and stacking technology as well as the FE-FET transistor and FE-RAM. Meanwhile, the development of lithography technology is also discussed. And a brief outlook on the future development of silicon integrated circuit technology is given.

Photo-rechargeable zinc-ion battery using highly ordered and vertically oriented C@VO2/ZnO microrod arrays

Development of photo-rechargeable batteries is a potential resolution for supplying off-grid solar power system in remote locations. Here, we present a photo-rechargeable zinc-ion battery (PRZIB) that can be directly recharged by the light without external photovoltaic cells and controllers. A highly ordered and vertically oriented ZnO microrod arrays (ZMRAs) were prepared using hydrothermal method in micron-scale patterned ZnO substrate defined by lithographic technology, which are used to incorporate with carbon encased vanadium oxide (C@VO2) nanocomposite to form a large specific surface area of three-dimensional network of C@VO2/ZnO heterojunction. PRZIB was assembled using C@VO2/ZMRAs structure as the photovoltaics as well as intercalation host for Zinc-ions, which demonstrates a photo-conversion efficiency of 3.3 % and gravimetric capacities of 286.0 mAh g−1 and 339.3 mAh g−1 at 500 mA g−1 in dark and light conditions. An excellent long-term cycling stability was achieved with a capacity retention of 88.79 % after 300 cycles at 1000 mA g−1 in dark condition. It is suggested that the distinctive morphologies and structure of C@VO2/ZMRAs provide effective strategies for enhancing photo-electrochemical redox reaction kinetics.

VR device with high resolution, high luminance, and low power consumption using 1.50‐in. organic light‐emitting diode display

AbstractWe fabricated a microdisplay with a 1.50‐in. organic light‐emitting diode (OLED) and a pixel density as high as 3207 ppi. An ideal display with high luminance, low power consumption, an ultrahigh aperture ratio, and a wide color gamut can be fabricated using a metal maskless lithography technology for patterning OLED layers and an oxide semiconductor large‐scale integration (OSLSI)/silicon LSI backplane. We designed a virtual reality device that exhibited less ghosting and a field of view of 90° or greater by combining the microdisplay and a novel pancake lens.

Lithography mask thermal and stress effect for the machine overlay compensation

With the continuous advancement of integrated circuit technology nodes, the degree of chip integration is increasing, and the requirements for critical dimensions and overlay errors are becoming more and more stringent. In recent years, near-field lithography technologies such as nanoimprint lithography and plasmonic lithography have made rapid progress; however, the challenge of compensating for their overlay has yet to be solved or systematic reports are lacking. This work offers an overlay compensation approach based on the theory of overlay and mask stress mechanics and thermodynamics by providing stress to the mask. The overlay analysis model and correction feedback mechanism based on mask compensation technology is carried out theoretically. This work establishes the relationship between the overlay compensation parameters and the mask stress by using strict calculation methods, quantitative characterization, and combining sensitivity analysis methods. Theoretical verification of various overlay distribution patterns demonstrates the efficiency of this feedback compensation strategy as well as the quantitative analytical calculation. It is verified that, under ideal conditions, the feedback technique may minimize the overlay error caused by mask thermal effects to ∼1.5 nm. This research presents a quantitative control mechanism for reducing overlay for near-field lithography, and it has substantial guiding implications for traditional lithography quantitative research on the influence of mask stress or temperature on overlay.