Litho Etch Research Articles

Middle of Line (MoL) Cleaning Challenges in Sub-20nm Node Device Manufacturing

In advanced technology nodes (sub 20nm), the gate & active contact architecture has become very complex. This architecture not only introduced new materials but also integrated additional patterning mask layers. This necessitated a separate Middle of Line (MoL) zone whereas conventionally contact integration used to be a Front End of Line (FEoL) process. This paper discusses wet cleaning challenges in MoL that were unforeseen with conventional contact architecture. Typical chemistries such as Sulfuric Peroxide Mixture (SPM), dilute Hydrofloric Acid (dHF), Aqua Regia, Standard Clean 1 (SC1), etc. that were used for contact cleaning or in salicidization process are found to be too aggressive due to smaller process window, shrinking Critical Dimensions (CD), and other challenges arising from overall tighter tolerances. As a result of device scaling, most of the MoL mask patterning is done with immersion lithography and double patterning techniques such as Litho-Etch Litho-Etch (LELE) are also needed. Immersion lithography is very sensitive to pre-litho backside and frontside particles which make pre-litho cleaning in MoL very critical as well. Also due to lack of high aspect ratio features in MoL (mostly contact holes), physical particle removal techniques such as droplet spray and MegaSonic can be very effectively used to achieve higher Particle Removal Efficiency (PRE). This paper summarizes such different scenarios & related challenges.

ASAP7: A 7-nm finFET predictive process design kit

We describe a 7-nm predictive process design kit (PDK) called the ASAP7 PDK, developed in collaboration with ARM Ltd. for academic use. The PDK is realistic, based on current assumptions for the 7-nm technology node, but is not tied to any specific foundry. The initial version assumes EUV lithography for key layers, a decision based on its present near cost-effectiveness and resulting simpler layout rules. Non-EUV layers assume appropriate multiple patterning schemes, i.e., self-aligned quadruple patterning (SAQP), self-aligned double patterning (SADP) or litho-etch litho-etch (LELE), based on 193-nm optical immersion lithography. The specific design rule derivation is explained for key layers at the front end of line (FEOL), middle of line (MOL), and back end of line (BEOL) of the predictive process modeled. The MOL and BEOL DRC rules rely on estimation of time dependent dielectric breakdown requirements using layer alignments determined with projected machine to machine overlay assumptions, with significant guard-bands where possible. A high density, low-power standard cell architecture, developed using design/technology co-optimization (DTCO), as well as example SRAM cells are shown. The PDK transistor electrical assumptions are also explained, as are the FEOL design rules, and the models include basic design corners. The transistor models support four threshold voltage (Vth) levels for both NMOS and PMOS transistors. Cadence Virtuoso technology files and associated schematic and layout editing, as well as netlisting are supported. DRC, LVS, and full parasitic extraction is enabled through Mentor Calibre decks.

Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era

For the first time, we present complete device threshold voltage (VT)-targeting methodology for FinFET SRAM in 10-nm technology, considering capacitance due to metal pattering and device variability to set target read current for different variants of SRAM architecture to determine technology high-density (HD) SRAM cell. The VT-targeting methodology brings into play the worst case read and write margins available for SRAM cell to determine nominal device VT by tuning the work function of metal gate. Analysis shows that for minimum leakage current, 112 SRAM cell is optimum, whereas for the same area of $0.0546~\mu $ $\mathrm{m}^{\mathrm {2}}$ with 50% higher leakage, 122 SRAM outperform by 5% and 20% improved read and write margins, respectively. The 122 SRAM as HD cell reduces the cost of the technology by sharing P-channel field effect transistor (PFET) and N-channel field effect transistor (NFET) VT mask with the high threshold voltage logic devices, whereas the 112 SRAM device shares only NFET VT mask. The 111 SRAM can achieve target performance at lesser area of $0.048~\mu $ $\mathrm{m}^{\mathrm {2}}$ by compromising read stability, which will result in lower yield. At 64-nm pitch, litho-etch litho-etch (LELE) double-patterned gate impacts device performance and alleviates variability; hence the read margin of SRAM cell should consider an additional $1\sigma _{\mathrm {\mathbf {rsnm}}}$ margin to retain the same yield in 10-nm-technology era.

Double Patterning Lithography Alignment and OVL-Control Strategy for 20nm Technology

Double patterning using 193 nm immersion lithography has been adapted as the solution to enable 20 nm technology nodes. In the Back end, Litho Etch Litho Etch (LELE) is considered as the most suitable process for this technology. The overlay control is one of the key figures for the successful realization of this technology. This paper presents a method called indirect alignment and indirect overlay measurement comparing with the common method (so called direct alignment and overlay the overlay (OVL) measurement) based on process complexity. While doing LELE, the common method need two or more films to get enough signal intensity for alignment measurement while the present method need only one film. In this paper, we will compare with the two overlay control methods and we also evaluate the risks for the present method and try to design a new APC control system to reduce the risks.

Sensitivity of Process Parameters on Pattern Formation of Litho–Cure–Litho–Etch Process

Semiconductor manufacturing has depended on the high resolution of optical lithography. As the wavelength becomes shorter for the resolution, the light source and optics become increasingly complex and expensive. Therefore, to extend optical lithography's useful life at greater resolution, the litho–cure–litho–etch (LCLE) process has been introduced as an alternative technique. In this study, the LCLE process is modelled and simulated to explore the pattern formation between the two lithography processes (litho 1 and litho 2). This process allows for the physical phenomena of pattern formation to be better understood. The sensitivity of simulation parameters for simulated profiles is analyzed by Taguchi analysis. Through the sensitivity of these easy-to-optimize parameters, LCLE lithography processes can be effectively predicted.

Sensitivity of Process Parameters on Pattern Formation of Litho–Cure–Litho–Etch Process

Sensitivity of Process Parameters on Pattern Formation of Litho–Cure–Litho–Etch Process

Pattern Freezing Process Free Litho–Litho–Etch Double Patterning

Double patterning technology based on existing ArF immersion lithography is considered as the most viable option for complementary metal oxide semiconductor (CMOS) node of 32 nm and below. Most of double patterning approaches previously described requires intermediate processing step such as hard mask etching, spacer material deposition, and resist pattern freezing. The requirement of these additional steps is now leading way to requests for throughput reduction and low cost for production for double patterning technology applications. In this paper, litho–litho–etch (LLE) double patterning without any intermediate processing steps is investigated to achieve narrow pitch resist imaging. The LLE options examined in this work are combinations of positive tone-negative tone and positive tone-positive tone photoresist double patterning process. These are the alternative processes in pattern freezing process free LLE double patterning. The goals of this work are to determine witch of these approaches is the most viable for future application and to confirm the patterning potential for 32 nm and below half pitch resist imaging.

Rigorous diffraction simulations of topographic wafer stacks in double patterning

Double patterning is regarded as a potential candidate to achieve the 32 nm node in semiconductor manufacturing. A key problem for a standard litho-etch–litho-etch (LELE) double patterning process is to evaluate and tackle the impact of the wafer topography resulting from the hardmask pattern on the second lithography step. In this paper, we apply rigorous electromagnetic field (EMF) solvers to investigate the wafer topography effects. At first, the studied 3D mask is split into two masks. The topography resulting from the exposure with the first split mask is described by a patterned hardmask. Based on that, the bottom antireflective coating (BARC) thickness of the second wafer stack is optimized. Alternatively, a two beam interference and the full diffraction spectrum of the second mask are used as the illumination of the wafer stacks, respectively. Finally, simulated 3D resist profiles for different BARC thicknesses are shown. The importance of wafer topography impact, the optimization of topographic wafer stacks, and the possible solutions to compensate for the impact of the wafer topography are discussed.