Linear Mixer Research Articles

Design and Analysis of Divide-by-4 Injection-Locked Frequency Divider Using Gain-Boosting Injection Balun and Dual Linear Mixer Techniques

Design and Analysis of Divide-by-4 Injection-Locked Frequency Divider Using Gain-Boosting Injection Balun and Dual Linear Mixer Techniques

MIX-NET: Deep Learning-Based Point Cloud Processing Method for Segmentation and Occlusion Leaf Restoration of Seedlings

In this paper, a novel point cloud segmentation and completion framework is proposed to achieve high-quality leaf area measurement of melon seedlings. In particular, the input of our algorithm is the point cloud data collected by an Azure Kinect camera from the top view of the seedlings, and our method can enhance measurement accuracy from two aspects based on the acquired data. On the one hand, we propose a neighborhood space-constrained method to effectively filter out the hover points and outlier noise of the point cloud, which can enhance the quality of the point cloud data significantly. On the other hand, by leveraging the purely linear mixer mechanism, a new network named MIX-Net is developed to achieve segmentation and completion of the point cloud simultaneously. Different from previous methods that separate these two tasks, the proposed network can better balance these two tasks in a more definite and effective way, leading to satisfactory performance on these two tasks. The experimental results prove that our methods can outperform other competitors and provide more accurate measurement results. Specifically, for the seedling segmentation task, our method can obtain a 3.1% and 1.7% performance gain compared with PointNet++ and DGCNN, respectively. Meanwhile, the R2 of leaf area measurement improved from 0.87 to 0.93 and MSE decreased from 2.64 to 2.26 after leaf shading completion.

Detection and validation of spatiotemporal snow cover variability in the Himalayas using Ku-band (13.5 GHz) SCATSAT-1 data

ABSTRACT The present study evaluates the potential of Ku-band Scatterometer Satellite-1 (SCATSAT-1) for quantification of spatiotemporal variability in snow cover area (SCA) over Himalayas (Himachal Pradesh) India. The SCA has been measured using dual-polarized (HH and VV) backscattered SCATSAT-1 data. Two classification approaches, i.e., Linear Mixer Model (LMM) and Artificial Neural Network (ANN) model have been used for the present study. Both available backscatter coefficients sigma-naught and gamma-naught have been considered for the estimation of SCA. To compute the seasonal snow cover trends for winter (2016‒2017 and 2017‒2018), a post-classification comparison (PCC) based change detection approach has been demonstrated on the classified dataset (LMM and ANN). The SCA maps have been validated using reference snow cover maps generated from the Moderate-resolution Imaging Spectroradiometer (MODIS) sensor. The final change-category maps have effectively mapped the snow cover variations with accuracy in between 83.01% and 95.33%. The results indicate the suitability of SCATSAT-1 for estimating the magnitude of snow extent over the Himalayas.

Wide-Locking Range RLC-Tank Balanced-Injection Divide-by-5 Injection-Locked Frequency Dividers Based on Harmonic Mixing

This article presents and analyzes a wide-locking range divide-by-5 injection-locked frequency divider (ILFD) manufactured in the TSMC 0.18- $\mu \text{m}$ processes. The ILFD uses the balanced injection method and uses the pure harmonic mixing approach at low injection power, and it is designed with an RLC dual-resonance resonator. The harmonic mixer relies on the self-generated second harmonic, which increases with injection power. Because of no narrowband filter as used in the linear mixer counterpart, the divide-by-5 ILFD uses a wideband design method. In addition, the ILFD enhances the divide-by-5 locking range via the overlapped dual-band locking ranges as verified by both experiment and simulation. At the drain–source bias ${V} _{\text{DD}}$ of 0.8 V and at the incident power of 0 dBm, the locking range of the divide-by-5 ILFD is 3.6 GHz, from the incident frequency 13.0–16.6 GHz with the percentage 24.3%. The core power consumption is 4.09 mW, and the die area is $1.02\times0.93$ mm2.

Wide-Locking Range Divide-by-4 Injection-Locked Frequency Divider Using Linear Mixer Approach

A novel divide-by-4 injection-locked frequency divider (ILFD) is proposed and was implemented in the TSMC $0.18~\mu \text{m}$ 1P6M CMOS process. Conventional harmonic mixer divide-by-4 ILFD has limited locking range, and this letter shows a wide locking range divide-by-4 ILFD designed with linear mixer technique. At the drain–source bias of 1 V and at the incident power of 0 dBm, the locking range is 3.9 GHz (36.28%) from 8.8 to 12.7 GHz at the power consumption of 3.61 mW. The free-running oscillation frequency is 2.6 GHz. The proposed ILFD is based on a cross-coupled voltage-controlled oscillator.

An In-Band Full-Duplex Radio Receiver With a Passive Vector Modulator Downmixer for Self-Interference Cancellation

In-band full-duplex (FD) wireless, i.e., simultaneous transmission and reception at the same frequency, introduces strong self-interference (SI) that masks the signal to be received. This paper proposes a receiver in which a copy of the transmit signal is fed through a switched-resistor vector modulator (VM) that provides simultaneous downmixing, phase shift, and amplitude scaling and subtracts it in the analog baseband for up to 27 dB SI-cancellation. Cancelling before active baseband amplification avoids self-blocking, and highly linear mixers keep SI-induced distortion low, for a receiver SI-to-noise-and-distortion-ratio (SINDR) of up to 71.5 dB in 16.25 MHz BW. When combined with a two-port antenna with only 20 dB isolation, the low RX distortion theoretically allows sufficient digital cancellation for over 90 dB link budget, sufficient for short-range, low-power FD links.

Divide-by-3 injection-locked frequency dividers using dual-resonance resonator

This paper exploits the application of dual-resonance LC resonator in the design of wide-locking-range injection-locked frequency dividers (ILFDs). The tail-injection and direct-injection divide-by-3 ILFD circuits in a standard CMOS process are realized with a pair of cross-coupled nMOSFETs with a dual-resonance LC-resonator. The locking range enhancement techniques such as linear mixer and quality-factor degradation are used to design wide-locking range divide-by-3 ILFD. At the incident power of 0 dBm the locking range of the divide-by-3 ILFD is 4.6 GHz (43.3 %), from the incident frequency 8.3 to 12.9 GHz.

Wide‐locking range divide‐by‐4 injection‐locked frequency divider using injection MOSFET DC‐biased above threshold region

SummaryA novel wide locking range divide‐by‐4 injection‐locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18 µm 1P6M CMOS process. The divide‐by‐4 ILFD uses two injection transistors in series and DC‐biased above threshold voltage and a frequency doubler to enhance the function of linear mixers. At the drain‐source bias of 0.9 V and at the incident power of 0 dBm, the locking range of the divide‐by‐4 is 2.6 GHz; from the incident frequency 12.2 to 14.8 GHz, the percentage is 19.26%. The core power consumption is 10.35 mW. The die area of ILFD is 1.026 × 0.943 mm2. Copyright © 2015 John Wiley & Sons, Ltd.

A Low Voltage, Low Power and Highly Linear CMOS Down-Conversion Gilbert Cell Mixer Using MGTR Method

A radio frequency (RF) low voltage and low power down conversion mixer with high linearity using TSMC 0.18-μm technology is presented which operates in 2.4 GHz Industrial Scientific and Medical (ISM) band. The local oscillator (LO) frequency is 2.1 GHz with an input power of 5 dBm, whereas IF frequency is 300 MHz. Multiple gated transistors (MGTRs) method is used to increase the linearity of Gilbert cell mixer. In this method an auxiliary transistor is used parallel to the transconductance stage transistor. This increases linearity by decreasing of transconductance stage transistor. The simulation results show an IIP3 improvement of 16.55 dBm. The proposed low power and highly linear mixer consumes a power of 4.46 mW from 1.8 V a supply voltage. The noise figure (NF) and gain conversion are about 13.8 dB and 9.11 dB, respectively.

CFD simulation of vertical linear motion mixing in anaerobic digester tanks.

Computational fluid dynamics (CFD) was used to simulate the mixing characteristics of a small circular anaerobic digester tank (diameter 6 m) equipped sequentially with 13 different plunger type vertical linear motion mixers and two different type internal draft-tube mixers. Rates of mixing of step injection of tracers were calculated from which active volume (AV) and hydraulic retention time (HRT) could be calculated. Washout characteristics were compared to analytic formulae to estimate any presence of partial mixing, dead volume, short-circuiting, or piston flow. Active volumes were also estimated based on tank regions that exceeded minimum velocity criteria. The mixers were ranked based on an ad hoc criteria related to the ratio of AV to unit power (UP) or AV/UP. The best plunger mixers were found to behave about the same as the conventional draft-tube mixers of similar UP.

The New Party Line: Power-Frequency Tradeoff in Linear BiCMOS Passive Mixers for Cellular Base Stations

This article will demonstrate how optimum device sizing is leveraged to design highly linear and low-noise mixers in various cellular base stations with bands ranging from 800 to 3,500 MHz. The device design approach demonstrated herein also shows the limits in achievable distortion performance for a given technology, enabling the system designer to make tradeoff evaluations between the various components in the system.

A wide‐locking ÷3 BiCMOS injection‐locked frequency divider using internal feedback

ABSTRACTA wide locking range divide‐by‐3 injection‐locked frequency divider (ILFD) using a standard 0.18‐μm SiGe 3P6M BiCMOS process is presented. The ÷3 ILFD circuit is realized with an n‐core MOS LC‐tank oscillator. The ILFD uses a push‐push signal circuit and two linear mixers with one radio‐frequency injection input port and one push‐push signal input port. An HBT is used to amplify the push‐push signal and extend locking range. The core power consumption of the ILFD core is 13.2 mW at the drain‐source voltage of 0.8 V. The divider's free‐running frequency is tunable from 3.079 to 3.163 GHz and at the incident power of 0 dBm, the locking range is 19.28%, from 8.9 to 10.8 GHz. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:493–497, 2014

A linear high-gain and low-power CMOS UWB mixer

This article presents the design process, and analysis of a high-linearity, high-gain, low-power and inductorless 3.1–4.8 GHz ultra-wideband (UWB) down conversion mixer in a 0.18 μm CMOS process with a 1.8 supply voltage. In the proposed structure, the linearity of the conventional Gilbert cell mixer is increased about 10 dBm without losing the conversion gain using the modified derivative superposition and current-bleeding techniques. Moreover, power consumption of the conventional mixer is significantly decreased. Besides, the conversion gain and S11 of the mixer are hand calculated and the validity of the analytical formulas is verified by simulation results.

A 35-to-83 GHz Multiconductor-Lines Signal Combiner for High Linear and Wideband Mixer

This letter proposes a broadband and low-loss multiconductor-lines signal combiner in 90 nm CMOS. The signal combiner consists of one broadside-coupled balun, two broadband in-phase power dividers, one edge-coupled balun, and four impedance-transformation lines. By using thin-film microstrip lines to avoid the loss from silicon substrate, the signal combiner has a simulated insertion loss of 8.1 dB and port-to-port isolations better than 42 dB from 35 to 83 GHz. The signal combiner is then integrated into a source-pumped mixer, and a -1±1.5-dB conversion gain and a 13 dBm average input IP3 at a 6.5 mW total dc power are achieved in measurements.

Wide-locking range ÷3 series-tuned injection-locked frequency divider

A new wide locking range series-tuned (ST) divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ÷3 ILFD circuit is realized with a ST cross-coupled n-core MOS LC-tank oscillator. Two direct-injection MOSFETs in series are used as a frequency doubler and a dynamic linear mixer to widen the locking range. The power consumption of the ILFD core is 10.56 mW. The divider's free-running frequency is tunable from 3.529 to 3.828 GHz by tuning the varactor's control bias, and at the incident power of 0 dBm the maximum locking range is 2.3 GHz (21.6 %), from the incident frequency 9.5 to 11.8 GHz. The operation range is 2.5 GHz (23.7 %), from 9.3 to 11.8 GHz.

LC-tank divide-by-4 injection-locked frequency divider using the second-order harmonic feedback

A low voltage, wide locking range and operation range divide-by-4 injection-locked frequency divider (ILFD) is proposed in the paper and the ILFD was fabricated in the TSMC 90 nm RF-CMOS process. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator (VCO) with a parallel-tuned LC resonator and a three-transistor composite that acts as a linear and nonlinear mixer. At a drain-source bias of 0.6 V and at an incident power of 0 dBm, the operation range of the divide-by-4 ILFD is 5.3 GHz, from the incident frequency 21.1 GHz to 26.4 GHz, and the percentage of operation range is 22.31%. The locking range of the divide-by-4 ILFD is 1.4 GHz, from the incident frequency 21.1 GHz to 22.5 GHz, and the percentage of locking range is 6.42%. The core power consumption is 2.58 mW. The die area is 0.86 × 0.75 mm2.

Graphene FETs for Zero-Bias Linear Resistive FET Mixers

In this letter, we present the first graphene FET operation for zero-bias resistive FET mixers, utilizing modulation of graphene channel resistance rather than ambipolar mixer operations, up to 20 GHz. The graphene FETs with a gate length of 0.25 μm have an extrinsic cutoff frequency fT of 40 GHz and a maximum oscillation frequency fMAX of 37 GHz. At 2 GHz, the graphene FETs show a conversion loss of 14 dB with gate-pumped resistive FET mixing, with at least > 10-dB improvement over reported graphene mixers. The input third-order intercept points (IIP3s) of 27 dBm are demonstrated at a local oscillator (LO) power of 2.6 dBm. The excellent linearity demonstrated by graphene FETs at low LO power offers the potential for high-quality linear mixers.

A differential BiCMOS divide-by-4 injection-locked frequency divider

A low power wide locking range divide-by-4 injection-locked frequency divider (ILFD) is proposed in the letter and was implemented in the TSMC 0.18 μm SiGe BiCMOS process. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator with an active inductor and a three-transistor composite consisted of two nMOSFETs and one pMOSFET to serve as an injection device with the function of linear and nonlinear mixers. At the supply voltage of 1.5 V and at the incident power of 0 dBm, the operation range of the divide-by-4 is 2.3 GHz, from the incident frequency 14.5 to 16.8 GHz, the percentage is 14.7%. The locking range of the divide-by-4 is 1.7 GHz, from the incident frequency from 14.6 to 16.3 GHz, the percentage is 11%. The core power consumption is 1.5 mW. The die area is 0.465 × 0.317 mm2. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2825–2828, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27204

Wideband divide-by-2 quadrature injection-locked frequency dividers with large output voltage swing

This letter presents a quadrature injection-locked frequency divider (QILFD) to achieve high-speed, wide-locking range, accurate quadrature output phases, and large output voltage swing.The QILFD consists of two differential top-series-injected injection-locked frequency dividers coupled by four parasitic bipolar junction transistors (BJTs). The MOSFET with the coupling BJT is used as a top-series RF injector and linear mixer. The proposed QILFD has been implemented with the TSMC 0.13-μm CMOS technology and the core power consumption is 6.02 mW at the supply voltage of 0.8 V. The operation range is from 9.2 to 12.8 GHz while the input power is 0 dBm. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2284–2287, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27089

A novel compact low-power direct conversion receiver for mobile UHF RFID reader

A novel direct conversion receiver with low cost and low power is implemented in a 0.18 μm 1P6M standard CMOS process for a Mobile UHF RFID reader. A highly linear active mixer with low flicker noise and low noise active load is proposed. An efficient and low cost on-chip DC offset voltage canceling scheme is adopted with a high-input-impedance four-input OPAMP to buffer the output of the DC offset canceller (DCOC) block. The receiver has a measured input 1 dB compression point of −2 dBm and a sensitivity of −72 dBm in the presence of the large leakage signal from the transmitter. Only occupying a silicon area of 2.5 mm2 and consuming 21 mA from a 1.8 V supply, the receiver makes the mobile UHF RFID reader to communicate with a transponder in a distance of 1 m conveniently.