Linear Feedback Shift Register Structure Research Articles

Multi-Layer QCA Shift Registers and Wiring Structure for LFSR in Stream Cipher with Low Energy Dissipation in Quantum Nanotechnology

Pseudorandom numbers (PRN) are used in various cryptographic applications, such as cryptographic protocols and stream ciphers. The most efficient hardware method used to generate PRNs is to use a Linear Feedback Shift Register (LFSR) structure, which is generally composed of a Shift Register (SR) and an XOR gate. The most important factors in designing the entire LFSR structure are design cost and energy efficiency, which are highly dependent on the SR structure. In the proposed study, the structural characteristics and problems of existing various types of SRs are presented, and new multi-layered serial-in-serial-out (SISO) and parallel-in-parallel-out (PIPO) SRs are proposed. In addition, we compare and analyze the area-time complexity, design cost, and energy dissipation through simulation using QCADesigner and QCADesigner-E. As a result, the proposed SISO and PIPO showed a performance improvement of more than 27% compared to the existing structure, which showed the best performance, and showed energy dissipation reduction rates of about 65% and 59%, respectively. In particular, we proposed multi-layer wiring that can reduce energy dissipation and verified through simulation that it can save up to 24.8%.

Quantum LFSR Structure for Random Number Generation Using QCA Multilayered Shift Register for Cryptographic Purposes.

A random number generator (RNG), a cryptographic technology that plays an important role in security and sensor networks, can be designed using a linear feedback shift register (LFSR). This cryptographic transformation is currently done through CMOS. It has been developed by reducing the size of the gate and increasing the degree of integration, but it has reached the limit of integration due to the quantum tunneling phenomenon. Quantum-dot cellular automata (QCA), one of the quantum circuit design technologies to replace this, has superior performance compared to CMOS in most performance areas, such as space, speed, and power. Most of the LFSRs in QCA are designed as shift registers (SR), and most of the SR circuits proposed based on the existing QCA have a planar structure, so the cell area is large and the signal is unstable when a plane intersection is implemented. Therefore, in this paper, we propose a multilayered 2-to-1 QCA multiplexer and a D-latch, and we make blocks based on D-latch and connect these blocks to make SR. In addition, the LFSR structure is designed by adding an XOR operation to it, and we additionally propose an LFSR capable of dual-edge triggering. The proposed structures were completed with a very meticulous design technique to minimize area and latency using cell interaction, and they achieve high performance compared to many existing circuits. For the proposed structures, the cost and energy dissipation are calculated through simulation using QCADesigner and QCADesigner-E, and their efficiency is verified.

Modifying LFSR of ZUC to Reduce Time for Key-Stream Generation

ZUC is stream-cipher which generates 32-bit key-stream by using 128-bit initial key and 123-bit initial vector. It encrypts the plaintext data to produce cipher-text data. The 128-EEA3 encryption and 128-EIA3 authentication algorithms are based on ZUC which are specified for use in 3GPP cellular communications systems. The algorithm is divided in three stages: LFSR (Linear Feedback Shift Register), Bit Reorganization (BR) and, Non-Linear Function. In this paper, we are going to discuss about our modifications proposed for LFSR along with small change in operation of Non-linear Function which can reduce time for generating key-stream. Many attacks based on weakness of LFSR due to its linearity are proposed which in turn makes ZUC susceptible to various attacks based on LFSR. As we know in the structure of LFSR, non-linearity is provided in last block of LFSR by feedback operation while all other being clocked with previous value of LFSR, so we have introduced bit-shifting and circular shift operations on few blocks of LFSR output of which will be taken as input to other blocks of LFSR.

Aliasing errors in Parallel Signature Analyzers

A Linear Feedback Shift Register (LFSR) can be used to compress test response data as a Signature Analyzer (SA). Parallel Signature Analyzers (PSAs) implemented as multiple input LFSRs are faster and require less hard ware overhead than Serial Signature Analyzers (SSAs) for compacting test response data for Built-In Self-Test (BIST) in IC or board-testing environments. However, the SAs are prone to aliasing errors because of some specific types of error patterns. An alias is a faulty output signature that is identical to the fault-free signature. A penetrating analysis of detecting capability of SAs depends strongly on mathematical manipulations, instead of being aware of some special cases or examples. In addition, the analysis should not be restricted to a particular structure of LFSR, but be appropriate for various structures of LFSRs. This paper presents necessary and sufficient conditions for aliasing errors based on a complete mathematical description of various types of Sas. An LFSR reconfiguration scheme is suggested which will prevent any allasing double errors. Such a prevention cannot be obtained by any extension of an LFSR.