Linear Feedback Shift Register Circuit Research Articles

High-performance LFSR circuit design based on XOR gates

The research discussed in this article is focused on analysing the effects of XOR gates based on different logic families, namely MOS Current Mode Logic (MCML), dynamic current logic, and PTL, on the performance of linear feedback shift register (LFSR) circuits. The aim of the study is to evaluate the power dissipation and critical path latency of the circuits while comparing the results with earlier works in the field. To achieve this, the researchers implemented the 3, 4, and 5-bit LFSR circuits using Verilog HDL code and synthesized them on the Cadence tool using 90nm CMOS technology. The study concludes that LFSR circuits based on XOR gates outperform previous LFSR circuits in terms of power dissipation. The research also offers a comparative analysis of the different types of XOR gates used in the LFSR circuits, highlighting the advantages and disadvantages of each type. The results of the study can be useful for researchers working in the field of circuit design, as well as for practitioners who are interested in developing low-power and efficient LFSR circuits.

Design of a 1.9 GHz low-power LFSR Circuit using the Reed-Solomon Algorithm for Pseudo-Random Test Pattern Generation

A linear feedback shift register (LFSR) has been frequently used in the Built-in Self-Test (BIST) designs for the pseudo-random test pattern generation. The higher volume of the test patterns and the lower test power consumption are the key features in the large complex designs. The motivation of this study is to generate efficient pseudo-random test patterns by the proposed LFSR and to be applied in the BIST designs. For the BIST designs, the proposed LFSR satisfied with the main strategies such as re-seeding and lesser test power consumption. However, the reseeding approach was utilized by the maximum-length pseudo-random test patterns. The objective of this paper is to propose a new LFSR circuit based on the proposed Reed-Solomon (RS) algorithm. The RS algorithm is created by considering the factors of the maximum length test patterns with a minimum distance over the time t. Also, it has been achieved an effective generation of test patterns over a stage of complexity order O (m log2 m), where m denotes the total number of message bits. We analysed our RS LFSR mathematically using the feedback polynomial function to decrease the area overhead occupied in the designs. The simulation works of the proposed RS LFSR bit-wise stages are simulated using the TSMC 130 nm on the Mentor Graphics IC design platform. Experimental results showed that the proposed LFSR achieved the effective pseudo-random test patterns with a lower test power consumption of 25.13 µW and 49.9 µs. In addition, proposed LFSR along with existing authors’ LFSR are applied in the BIST design to examine their power consumption. Ultimately, overall simulations operated with the highest operating frequency environment as 1.9 GHz.

Analysis and Design of the Pseudo-Random Bit Generator in the Technology of Quantum-Dot Cellular Automata

One of the novel technologies in the implementation of digital circuits is Quantum-Dot Cellular Automata (QCA) nanotechnology. This technology, which has been introduced over two decades ago, can be a great alternative to today’s CMOS chips. The main advantages of this technology include low occupation area and ultra-low power consumption. This paper presents an effective design and arrangement of one of the methods of pseudo random bit generator which is called linear feedback shift register (LFSR) in the technology of quantum cellular automata. In this research, using the D-latch and level to edge converter, a flip-flop is designed. The proposed D flip-flop and an XOR gate are used to design three new LFSR circuits in QCA technology. The simulation results show that the proposed designs have stable and useful structures in terms of area, latency and complexity. Simulations show that the first proposed 3-bit pseudo random code design has 233 cells, 4 clock delay cycles, and 0.27μm2 occupied area while the second proposed 3-bit design has 175 cells, 4 clock delay cycles, and 0.23 μm2 occupied area. In addition, the third proposed 3-bit LFSR has 188 cells, latency of 4 clock cycle and occupied area of 0.24 μm2. Power analysis are done for all of the designs.

BIST-Based Low Power Test Vector Generator and Minimizing Bulkiness of VLSI Architecture

In several pseudorandom built-in self-test (BIST) circuits, the applied test vectors will be generated by a linear feedback shift register (LFSR). This type of test pattern generator (TPG) may generate some repeated test patterns, which unnecessarily increases the test power without contributing much to the fault coverage. Based on the vast designs of TPG engine, the chip area also increases by contributing for the overall power consumption of the IC. This paper presents an approach called low power — bit complements test vector generation (LP-BCTVG) technique with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. In order to reduce the test power, the LP-BCTVG inserts appropriate intermediate vectors in between consecutive test vectors generated by LFSR circuit. Hence, the application of final output vectors of LP-BCTVG circuit over circuit under test decreases the test power compared with LFSR-based BIST. By complementing the output bits of LP-BCTVG, we can reduce the bulkiness of TPG engine approximately by half. This further contributes to the reduced IC size. The obtained simulation results prove that this technique can reduce the overall test power consumption along with better fault coverage when compared with LFSR-based BIST and other recent methods. Here, the proposed approach has been tested on several ISCAS’85, ISCAS’89 and ITC’99 benchmark circuits.

A lightweight method of data encryption in BANs using electrocardiogram signal

Body area network (BAN) is a key technology of solving telemedicine, where protecting security of vital signs information becomes a very important technique requirement. The traditional encryption methods are not suitable for BANs due to the complex algorithm and the large consumption. This paper proposes a new encryption method based on the QRS complex of the ECG signal, which adopts the vital signs from the BAN system to form the initial key, utilizes the LFSR (Linear Feedback Shift Register) circuit to generate the key stream, and then encrypts the data in the BANs. This new encryption method has the advantages of low energy consumption, simple hardware implementation, and dynamic key updating.

Selected Mapping Technique for PAPR Reduction Without Side Information Based on m-Sequence

Selected mapping (SLM) is a technique for reducing the high peak-to-average power ratio (PAPR) in which a suitable signal is selected among a set of alternative signals which all indicate alike information. The chief drawback existing in this method is that transmitter is compelled to send several additional bits called side information (SI) for each data block in order that recovering at the receiver side can be possible. In this paper, we present a novel SLM scheme by using the linear feedback shift register circuit and m-sequence named MSLM technique by which any side information bit is not explicitly sent. In MSLM, The basic idea is to fit the side information into transmitted symbols based upon which some special locations in the transmitted data block are expanded, i.e. some transmitted symbols are extended. In the receiver side, by using some properties of m-sequence the SI bits can be detected. We present the example of our method for an OFDM system through the use of 16-QAM modulation and different m-sequences and finally, concerned results are illustrated from the view point of bit error rate, probability of detection failure and PAPR reduction.

Detection of M-Sequences from Spike Sequence in Neuronal Networks

In circuit theory, it is well known that a linear feedback shift register (LFSR) circuit generates pseudorandom bit sequences (PRBS), including an M-sequence with the maximum period of length. In this study, we tried to detect M-sequences known as a pseudorandom sequence generated by the LFSR circuit from time series patterns of stimulated action potentials. Stimulated action potentials were recorded from dissociated cultures of hippocampal neurons grown on a multielectrode array. We could find several M-sequences from a 3-stage LFSR circuit (M3). These results show the possibility of assembling LFSR circuits or its equivalent ones in a neuronal network. However, since the M3 pattern was composed of only four spike intervals, the possibility of an accidental detection was not zero. Then, we detected M-sequences from random spike sequences which were not generated from an LFSR circuit and compare the result with the number of M-sequences from the originally observed raster data. As a result, a significant difference was confirmed: a greater number of “0–1” reversed the 3-stage M-sequences occurred than would have accidentally be detected. This result suggests that some LFSR equivalent circuits are assembled in neuronal networks.

High-Speed Parallel Architectures for Linear Feedback Shift Registers

Linear feedback shift register (LFSR) is an important component of the cyclic redundancy check (CRC) operations and BCH encoders. The contribution of this paper is two fold. First, this paper presents a mathematical proof of existence of a linear transformation to transform LFSR circuits into equivalent state space formulations. This transformation achieves a full speed-up compared to the serial architecture at the cost of an increase in hardware overhead. This method applies to all generator polynomials used in CRC operations and BCH encoders. Second, a new formulation is proposed to modify the LFSR into the form of an infinite impulse response (IIR) filter. We propose a novel high speed parallel LFSR architecture based on parallel IIR filter design, pipelining and retiming algorithms. The advantage of the proposed approach over the previous architectures is that it has both feedforward and feedback paths. We further propose to apply combined parallel and pipelining techniques to eliminate the fanout effect in long generator polynomials. The proposed scheme can be applied to any generator polynomial, i.e., any LFSR in general. The proposed parallel architecture achieves better area-time product compared to the previous designs.

Group parity prediction scheme for concurrent testing of linear feedback shift registers

A group parity prediction scheme which can be used for concurrent testing of linear feedback shift register circuits is described.