We have expanded the method in a recent note by Koniges and Leith [ 1 ] for a direct jump to any desired k th element κ k of the standard linear congruential random number generator specified by Eqs. (1) and (2). The digits of k (base b) in Eq. (6) are indices for selecting elements from two precalculated arrays, P and S, Eqs. (6) and (7). These elements are combined in Eqs. (10) and (11) to give the addends of κ k = κ k + Ω k . The choice of the base b determines the number of digits in k (base b). For each nonzero digit, the evaluation of Eqs. (10) and (11) require two multiplications (mod m), and one add. The larger the choice for b, the fewer the digits in k (base b), and the less the arithmetic needed to evaluate Eqs. (10) and (11). For modulus m = 2 48, values of b = 2, 8, and 256 require at most 48, 16, and 6 multiplications, respectively, to evaluate Eq. (10). The expected number of multiplications is somewhat less. As noted above, only the nonzero digits of k lead to modular arithmetic calculations (zero digits imply the addition of zero and/or multiplication by unity). For a random k, base b, the probability that a random bit is nonzero is (b − 1) b . Thus we find that the expected number of multiplications to evaluate Eq. (10) for b = 2, 8, or 256 drops to 24, 14, or 5.98, respectively. The drawback for very large base b is the storage needed for the precalculated P and S arrays, Eqs. (8) and (9). Each has b( J+ 1) elements, where J+ 1 is the maximum number of digits in k (base b). For m = 2 48 , and b = 2, 8, 256, there are respectively 2 × 48 = 96, 8 × 15 = 120, and 256 × 6 = 1536 elements in P and in S. If b is further increased, then each array size b( J+ 1) grows rapidly. On the other hand, the J+ 1 number of multiplications (mod m) needed to evaluate Eq. (10) decreases slowly. We suggest that for a 48-bit machine word length b = 256 is a good compromise between table size and achievable speedup. For a standard generator with zero additive term using base 256 reduces the overall operations count from 48 if tests, 48 register shifts, 24 multiplies, and 72 logical ands to 6 register shifts, 5.98 multiplies, and 11.98 logical ands, yielding more than a fourfold increase in speed over the base 2 case.