Line Buffer Research Articles

The Challenges of Line Buffers: Issues and Methods

The Challenges of Line Buffers: Issues and Methods

The conversion of the reinforced concrete post-war brownfield sites into greenfields: Green line buffer zone of Cyprus

Brownfield areas are hazardous areas that arise as a result of the disuse of industrial, commercial, and residential buildings, which pose an obstacle to planning and decision-making mechanisms for the regions in which they are located in terms of environment and energy, and are a global problem for settlements. In planning studies where sustainability principles are taken into account, both abandoned reinforced concrete structures and abandoned traditional structures that contribute to natural life should be considered together. Brown field structures built with traditional and reinforced concrete materials can be seen in the green line region of the island of Cyprus. Converting abandoned building areas built from concrete material remaining in the unused buffer zone after the war on the island into green corridors is important to ensure sustainability. In this context, the study was evaluated in line with the Wheeler Sustainability Principles, the weight of each marker was determined in line with the literature review and local expert reports, and a road map that could be used to transform brown areas into green areas was created. This study both contributes to the limited existing literature and reveals the effects of energy and environmental sustainability in abandoned areas.

ON RELOCATION OF SETTLEMENT AFTER THE CIANJUR EARTHQUAKE AND LANDSLIDE 2022

An Earthquake and landslide occurred in Cianjur, Indonesia, in November 2022. This resulted in a lot of losses, both fatalities and the disappearance of some settlements. Relocation would be obligatory as post-disaster mitigation policies for areas with highest disaster threats. This research was conducted to find its relocation areas. The method used is overlay and scoring by utilizing GIS applications. The used data are rainfall data, slope, geological maps, Cianjur earthquake hazard maps, fault line buffering, and supervised classification of land cover/use maps. Analysis of the results in the form of landslide hazard maps and disaster safety maps. The search for the expected relocation area is carried out by overlaying a disaster-safe map with residential areas, so that a post-disaster residential relocation recommendation map is produced with five classes, namely very good, good, medium, bad, and very bad. An analysis is also carried out for directions for the use of the affected area for the very bad class used as a protected area and no buildings are allowed on it. Bad class is not allowed to live on it, but can be used for social activities, plantations and paddy fields. The moderate vulnerability class can still be used as a residence, economic centre, or other social activities. Meanwhile, the safe and very safe vulnerability classes do not have any land use restrictions.

AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture and Accelerator-Aware Pruning.

Convolutional neural networks (CNNs) play a crucial role in many EdgeAI and TinyML applications, but their implementation usually requires external memory, which degrades the feasibility of such resource-hungry environments. To solve this problem, this paper proposes memory-reduction methods at the algorithm and architecture level, implementing a reasonable-performance CNN with the on-chip memory of a practical device. At the algorithm level, accelerator-aware pruning is adopted to reduce the weight memory amount. For activation memory reduction, a stream-based line-buffer architecture is proposed. In the proposed architecture, each layer is implemented by a dedicated block, and the layer blocks operate in a pipelined way. Each block has a line buffer to store a few rows of input data instead of a frame buffer to store the whole feature map, reducing intermediate data-storage size. The experimental results show that the object-detection CNNs of MobileNetV1/V2 and an SSDLite variant, widely used in TinyML applications, can be implemented even on a low-end FPGA without external memory.

Conserving habitat for migratory ungulates: How wide is a migration corridor?

Abstract Conserving migratory ungulates relies on the analysis of GPS collar data and associated maps of migration corridors to inform management and policy actions. Current methods for identifying migratory corridors use complex statistical models designed to account for movement uncertainty rather than estimating the amount of space required by animals to migrate. Furthermore, such methods can complicate conservation efforts by producing highly variable corridor widths and non‐contiguous corridors that do not fully connect seasonal ranges. To remedy, we propose an intuitive line buffer approach for delineating individual migration corridors that is simple to implement and focuses on the functional corridor widths needed by migratory ungulates. By buffering a line that connects successive GPS locations, we can delineate individual migration corridors with consistent widths that are robust to variable parameters (GPS fix rate, travel speed, tortuosity) and provide contiguous connection between seasonal ranges. Using a combination of expert knowledge, simulation and 10‐min GPS collar data collected from mule deer (Odocoileus hemionus) and pronghorn (Antilocapra americana), we suggest 400–600 m are reasonable estimates of functional migration corridor widths for individuals of those species. Synthesis and applications. Our line buffer approach is intended to simplify migration corridor delineation, improve transparency and encourage a broader discussion of functional corridor widths. These considerations help advance efforts to conserve habitat within migration corridors and prioritize conservation efforts within a single corridor or across multiple corridors.

Flexible Convolver for Convolutional Neural Networks Deployment onto Hardware-Oriented Applications

This paper introduces a flexible convolver capable of adapting to the different convolution layer configurations of state-of-the-art Convolution Neural Networks (CNNs). The use of two proposed programmable components achieves this adaptability. A Programmable Line Buffer (PLB) based on Programmable Shift Registers (PSRs) allows the generation of the required convolution masks required for each processed CNN layer. The convolution layer computing is performed through a proposed programmable systolic array configured according to the target device resources. In order to maximize the device resource usage and to achieve a shortened processing time, the filter, data, and loop parallelisms are leveraged. These characteristics allow the described architecture to be scalable and implemented on any FPGA device targeting different applications. The convolver description was written in VHDL using the Intel Cyclone V 5CSXFC6D6F31C6N device as a reference. The experimental results show that the proposed computing method allows the processing of any CNN without requiring special adaptation for a specific application since the standard convolution algorithm is used. The proposed flexible convolver achieves competitive performance compared with those reported in related works.

Performance analysis of cognitive wireless retrial queueing networks with admission control for secondary users

ABSTRACT This paper designs and analyzes a novel single-channel cognitive radio retrial queueing network wherein a waiting line buffer is deployed for secondary users (SUs). A finite source system generates the primary users (PUs). Apart from these, PUs having preemptive priority over SUs, the effect of retrial/repeated attempts of PUs is taken into consideration. In such a system, the stability condition and the joint steady-state probability distribution of PUs and SUs are studied by using the matrix-analytic method. Several performance metrics of interest, such as blocking probability, throughput, mean waiting time, etc., have been determined. The first-passage time to reach a congestion level in the SUs waiting line buffer and its related characteristics are investigated by employing the first-step principle. In addition, correlation coefficients for various events of SUs and PUs during this period have been assessed. Finally, extensive numerical results are presented graphically for the system insights.

Scale effects of multi-medium heavy metals in response to landscape indices in the Yuan River, China

Heavy metals in river basins can affect the entire ecosystem through water recycling. Different heavy metals are significantly affected by riparian landscape patterns due to the difference of source and migration processes, while the intensity of impact is directly influenced by the spatial scale of landscape patterns. Here, we employ correlation analyses (CA) and redundancy analyses (RDA) to determine spatial scales for which multi-medium heavy metals (Cr, Mn, Cu, Zn, As, Cd and Pb) are most sensitive landscape indices in the riparian zone of the Yuan River. Results show that the most sensitive spatial scales for dissolved heavy metals were the 300 m line buffer in the wet season and catchments in the dry season. The most sensitive spatial scales for suspended particulate heavy metals were catchments in the wet season, and the 300 m and 500 m line buffers in the dry season. However, correlations between heavy metals in sediment and landscape indices were unclear at all spatial scales. The spatial scales of the 100 m point buffer and catchments showed the highest explained variances for all media. The most important landscape indices for dissolved heavy metals were ENN_MN (Mean Euclidean Nearest Neighbor Distance) and LPI (Largest Patch Index), and SHDI (Shannon's Diversity Index) and ED (Edge Density) for particulate heavy metals. More accurate spatial scale effects of landscape indicators can provide data and reference for similar watershed studies.

Reconfigurable and hardware efficient adaptive quantization model-based accelerator for binarized neural network

Binarized neural networks (BNNs) architecture play a vital role in the development of deep learning accelerator for memory-constrained IoT devices. However, the cost-efficiency of the domain-specific accelerators still requires a simplified structure to enhance the computing performance of BNNs. We propose and present a reconfigurable BNN accelerator to improve the computing speed through channel amplitude and an adaptive spatial amplitude model. To reduce the redundant operations in the binarization of matrix multiplication, we introduce the channel amplitude model for BNN convolution functions. The adaptive spatial amplitude is implemented with the help of a matrix multiplication layer with 3 × 3 convolutions to get spatial information and increases the computation speed. For hardware implementation, the channel amplitude conversion is deployed through XNOR-popcount convolutions of each layer. The performance results of our proposed accelerator provide 2–10 × line buffer efficiency, 1.6–3.7 × processing frequency enhancement, and 2.35 × processing element reduction compared with existing baselines using VGG-16 based FPGA implementation.

A Hybrid Dehazing Method and its Hardware Implementation for Image Sensors

The demand for image dehazing is ever-increasing in image sensor based outdoor systems such as self-driving vehicles, automatic driver assistance, and in highway monitoring and analytics. These applications require dedicated hardware solution to meet high frame-rate and low power constraints. Previously, a few prior based hardware dehazing methods have been presented. However, they produce artifacts in the restored images due to the failure of the underlying assumptions. To address this problem and to meet the stringent requirements, a data-driven image dehazing approach based on convolutional neural network (CNN) and dark channel prior (DCP) is proposed that automatically learns the important features and produces better results. The proposed method is hardware friendly and its hardware implementation is also presented. The design employs few line buffers to store activations and eliminates the requirement of off-chip memory like dynamic random-access memory (DRAM). Field programmable gate array (FPGA) and application specific integrated circuit (AISC) implementations show that the architecture is highly suitable for application scenarios with constrained computational resources, low memory, and tight power budget. The quantitative analysis shows more than 11% average PSNR improvement in image quality on standard datasets as compared to the state-of-the-art hardware methods while consuming comparable hardware resources and power.

Real-time FPGA-based implementation of the AKAZE algorithm with nonlinear scale space generation using image partitioning

The first step in a scale invariant image matching system is scale space generation. Nonlinear scale space generation algorithms such as AKAZE, reduce noise and distortion in different scales while retaining the borders and key-points of the image. An FPGA-based hardware architecture for AKAZE nonlinear scale space generation is proposed to speed up this algorithm for real-time applications. The three contributions of this work are (1) mapping the two passes of the AKAZE algorithm onto a hardware architecture that realizes parallel processing of multiple sections, (2) multi-scale line buffers which can be used for different scales, and (3) a time-sharing mechanism in the memory management unit to process multiple sections of the image in parallel. We propose a time-sharing mechanism for memory management to prevent artifacts as a result of separating the process of image partitioning. We also use approximations in the algorithm to make hardware implementation more efficient while maintaining the repeatability of the detection. A frame rate of 304 frames per second for a 1280 times 768 image resolution is achieved which is favorably faster in comparison with other work.

Fast Thumbnail Extraction for H.264/AVC, HEVC and VP9

In this paper, we propose a partial decoding method with limited memory usage for high-speed thumbnail extraction. The proposed method performs a partial inverse transform and a partial intra prediction in order to reconstruct pixels for intra prediction and thumbnails. Thereafter, the reconstructed pixels at the bottom and right line of the block are stored in the line buffer and the thumbnail buffer without being stored in the decoded picture buffer with full resolution. H.264/AVC, HEVC and VP9 video codecs have different coding structures, prediction and transforms; however, the proposed algorithm can be applied to the corresponding codecs in the same manner. In order to evaluate the performance of the proposed method, we implemented the proposed algorithm for H.264/AVC, HEVC and VP9. We found that the thumbnail extraction time of the proposed method decreased by 66% in H.264/AVC, 52% in HEVC and 48% in VP9 as compared to the full decoding method.

Digital media zero watermark copyright protection algorithm based on embedded intelligent edge computing detection.

With the rapid development of computer technology and network communication technology, copyright protection caused by widely spread digital media has become the focus of attention in various fields. For digital media watermarking technology research emerge in endlessly, but the results are not ideal. In order to better realize the copyright identification and protection, based on the embedded intelligent edge computing detection technology, this paper studies the zero watermark copyright protection algorithm of digital media. Firstly, this paper designs an embedded intelligent edge detection module based on Sobel operator, including image line buffer module, convolution calculation module and threshold processing module. Then, based on the embedded intelligent edge detection module, the Arnold transform of image scrambling technology is used to preprocess the watermark, and finally a zero watermark copyright protection algorithm is constructed. At the same time, the robustness of the proposed algorithm is tested. The image is subjected to different proportion of clipping and scaling attacks, different types of noise, sharpening and blur attacks, and the detection rate and signal-to-noise ratio of each algorithm are calculated respectively. The performance of the watermark image processed by this algorithm is evaluated subjectively and objectively. Experimental data show that the detection rate of our algorithm is the highest, which is 0.89. In scaling attack, the performance of our algorithm is slightly lower than that of Fourier transform domain algorithm, but it is better than the other two algorithms. The Signal to Noise Ratio of the algorithm is 36.854% in P6 multiplicative noise attack, 39.638% in P8 sharpening edge attack and 41.285% in fuzzy attack. This shows that the algorithm is robust to conventional attacks. The subjective evaluation of 33% and 39% of the images is 5 and 4. The mean values of signal to noise ratio, peak signal to noise ratio, mean square error and mean absolute difference are 20.56, 25.13, 37.03 and 27.64, respectively. This shows that the watermark image processed by this algorithm has high quality. Therefore, the digital media zero watermark copyright protection algorithm based on embedded intelligent edge computing detection is more robust, and its watermark invisibility is also very superior, which is worth promoting.

Mixed Flow Assembly Line Balancing Problem Considering Material Supply Strategy

With the capacity limitation of the assembly line buffer area, a method for solving the mixed flow assembly line balancing problem considering material supply strategy is proposed. This paper analyzes the changes in material transportation time and assembly time due to different supply strategies, and proposes a method for jointly modeling the assembly line balancing and material supply problem. In the case of meeting the production cycle, with the buffer area capacity as the limit and the shortest production operation time as the goal, a joint optimization model including material handling time, material transportation time and assembly line working time is established, and the model is designed for the established model Genetic algorithm with piecewise coding. Finally, the proposed algorithm was evaluated using a workshop raw date， the simulation results show that although the indirect supply cost is relatively more than the direct supply, it can effectively alleviate the problem of the capacity limitation of the buffer area.

Generalized Buffering Algorithm

The existing buffers algorithms cannot effectively to meet the demands of high accuracy of buffer analysis in practice although many efforts have been made in the past 60 years. A generalized buffering algorithm (GBA) is presented, which considers the geometric distance and the attribute characteristics of all instances within buffer zone. The proposed algorithm includes three major steps: (1) select and initialize target instance; (2) determine buffer boundary points through mining homogeneous pattern; (3) “smoothly” connect buffer boundary points to generate the generalized buffer zone. The details for the generations of the generalized point buffer (GPIB) zone, the generalized line buffer (GLB) zone, and the generalized polygon buffer (GPLB) zone are discussed. Two dataset are used to validate the performances of the proposed GBA. Six parameters are applied as indexes to evaluate the proposed algorithm. The experimental results discovered that (1) the GBA is close to the tradition buffering algorithm (TBA) when the angle increment ( $\Delta \varphi$ ) in GPIB, line increment ( $\Delta L$ ) in GLB, and arc length increment ( $\Delta S$ ) in GPLB approach to zero, respectively; (2) the proposed GBA can accurately reflect the real situation of the buffering zone, and improve the deficiency and accuracy of TBA in real application.

Vision Inspection and Correction for DDI Protective Film Attachment

DDI(Display Driver IC) are used to drive numerous pixels that make up display. For stable driving of DDI, it is necessary to attach a protective film to shield electromagnetic waves. When the protective film is attached, defects often occur if the film is inclined or the center point is not aligned. In order to minimize such defects, an algorithm for correcting the center point and the inclined angle using camera image information is required. This technology detects the corner coordinates of the protective film by image processing in order to correct the positional defects where the protective film is attached. Corner point coordinates are detected using an algorithm, and center point position finds and correction values are calculated using the detected coordinates. LUT (Lookup Table) is used to quickly find out whether the angle is inclined or not. These algorithms were described by Verilog HDL. The method using the existing software requires a memory to store the entire image after processing one image. Since the method proposed in this paper is a method of scanning by adding a line buffer in one scan, it is possible to scan even if only a part of the image is saved after processing one image. Compared to those written in software language, the execution time is shortened, the speed is very fast, and the error is relatively small.

Best management practices scenario analysis to reduce agricultural nitrogen loads and sediment yield to the semiarid Mar Menor coastal lagoon (Spain)

Agriculture is a major source of diffuse pollution, where nitrogen and sediment pollution of water bodies are its main associated environmental impacts. Best management practices are effective tools for preventing and minimizing water pollution. Water quality models and model-based scenario analyses are useful tools for assessing impacts of best management practices and to identify appropriate strategies on the watershed scale. This study was conducted in the southernmost Mar Menor basin, one of the largest saltwater coastal lagoons in Europe and threatened by diffuse nutrient and sediment export from the agricultural landscape. This study evaluates the impact of several management practices on nitrogen and sediment loads, and horticultural crop yield, to identify an appropriate management strategy on the watershed scale. Both structural and nonstructural management practices scenarios were evaluated: three scenarios representing field operations, two coastal line buffers, a new fertilizer management strategy and a change in the productive cultivation system from three-crop rotation to two-crop rotation. Each management practice reduced a certain type of diffuse pollution and, therefore, a combined set of changed management practices is necessary to cope with all agricultural pollution types. Contour farming, combined with hedgerow field borders, was effective in sediment yield and surface organic nitrogen export reduction terms, while improved fertilizer management reduced surface nitrate export and leaching with minimal impacts on crop yields.

MCFD: A Hardware-Efficient Noniterative Multicue Fusion Demosaicing Algorithm

Color demosaicing is an essential step in the camera image processing pipeline, especially on hardware platforms for real-time video applications. Though many demosaicing algorithms have been proposed in the past two decades, there remains a substantial gap between industrial needs and academic research. On one hand, industry requires a high perceptual quality, artifact-free, and low-cost demosaicing algorithm that is noniterative and small window based ready to be implemented on a hardware platform with a limited line buffer. On the other hand, academia is targeting high PSNR/SSIM, with the computation cost and line buffer receiving second priority, and often a frame buffer and iterative operation are used. The cost, large line buffer and iteration requirement make most existing demosaicing algorithms inapplicable on hardware platforms. In this paper, we introduce a novel low-cost demosaicing algorithm to narrow the gap. We keep the operation window size and computation cost as the first priority and achieve both high PSNR/SSIM and visual perceptual quality compared to previous state-of-the-art methods on standard test datasets. We fully investigate the a priori knowledge of natural scene raw images and find several key cues that are beneficial to demosaicing. Our demosaicing algorithm is a smart fusion of these useful cues. Furthermore, we solve typical demosaicing issues that occur in many traditional methods, including false color artifacts, T-section closing, and zippering artifacts. The proposed method has no learning stage, no iteration operation, a small line buffer and a limited number of parameters, so it can easily be applied to hardware platforms.

Operation task extraction method and application of rice operation machinery in South China based on GNSS

According to the characteristics of rice planting and rice operation machinery in South China, the paper discusses how to use the satellite of the operation machinery to position trajectory information, to extract operation task by field based on the clustering algorithm of OPTICS, and to calculate the operation area by broken line buffer algorithm. The paper also discusses about parameter setting of OPTICS. The accuracy of extracting tasks by field can be over 84%. When the area of each task is over 3 mu (0.2 hectares), the calculation accuracy can reach over 95%. On the surface of practical application in Guangdong Province in recent three years, the algorithm can meet the requirements of operation charging and government subsidy giving, and realize accurate task differentiation and area calculation.

Algorithm and Architecture Design of FAST-C Image Corner Detection Engine

First-in–first-out (FIFO) line buffers occupy considerable logic gates and consume significant power of the feature from accelerated segment test (FAST) image corner detection engine. In this study, a FAST-Chip (FAST-C) engine is proposed to eliminate these drawbacks. It comprises three core techniques: arch pixel estimation (APE), hardware-efficient line buffer (HLB), and interleaving-based parallel access (IPA). APE can save three line buffers using gradient information for pixel prediction. With APE, the number of line buffers can be saved by 33%. HLB effectively organizes static random access memories (SRAMs) as line buffers to store reference pixels rather than FIFO. It demands less power and fewer logic gates. IPA makes the FAST-C engine have regular data paths and smooth data scheduling, keeping hardware throughput. Experiment results show that the accuracy difference between FAST and FAST-C is as minor as 2.29%. The proposed FAST-C engine is implemented using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18- $\mu \text{m}$ CMOS process with a logic gate count of 223k, where the line buffers are included. Its frequency is 613 MHz with a power consumption of 1.18 W. Its maximum throughput can sufficiently support $3840\times 2.160$ (4k) @ 60 frames per second (fps). Compared with sophisticated FAST engines, the FAST-C engine presents outstanding energy efficiency (EE) and area efficiency (AE).