Lifetime Of SSD Research Articles

Improving the performance and lifetime of TLC SSD by leveraging flash level disparities

Improving the performance and lifetime of TLC SSD by leveraging flash level disparities

Improving the performance and lifetime of TLC SSD by leveraging flash level disparities

Improving the performance and lifetime of TLC SSD by leveraging flash level disparities

Extending the lifetime of NAND flash-based SSD through compacted write

In the traditional file system, the partial page write will result in internal fragmentation and write amplification of NAND flash-based SSDs due to the page-alignment of write. Although large page sizes are useful for increasing the flash capacity and throughput, they may decrease the performance and lifetime of flash storage systems for the frequent partial page writes. After analysing the various realistic workload traces, we observe that the partial page writes are common for those heads and tails of large write requests. This observation makes compacted write possible, which compresses two partial page writes from the same large write request into one page before data are written into flash. Therefore, we propose a compacted write for page-level FTL scheme, called CWFTL, to extend the lifetime of SSD. The experiment results show that CWFTL really reduces the times of data written to flash and the average read/write response time.

Extending the lifetime of NAND flash-based SSD through compacted write

Extending the lifetime of NAND flash-based SSD through compacted write

Exploiting Data Longevity for Enhancing the Lifetime of Flash-based Storage Class Memory

This paper proposes to exploit the capability of retention time relaxation in flash memories for improving the lifetime of an SLC-based SSD. The main idea is that as a majority of I/O data in a typical workload do not need a retention time larger than a few days, we can have multiple partial program states in a cell and use every two states to store one-bit data at each time. Thus, we can store multiple bits in a cell (one bit at each time) without erasing it after each write -- that would directly translates into lifetime enhancement. The proposed scheme is called Dense-SLC (D-SLC) flash design which improves SSD lifetime by 5.1X--8.6X.

Adaptive ECC Scheme for Hybrid SSD’s

In recent years, multi-level cell flash memory (MLC) has been widely adopted in solid state drives (SSD’s) as the major storage medium due to its lower cost and higher density, compared with single-level cell flash memory (SLC). However, MLC has reliability concerns since it has lower endurance and higher disturb failure rate. Researchers thus proposed SLC/MLC hybrid SSD to exploit the advantages of SLC and MLC by separating frequently updated data in SLC and seldom modified data in MLC. In this paper, we propose an adaptive error correction code (ECC) scheme with four ECC levels to enhance the reliability of SSD’s. Different from past researches, SLC is dedicated for the management of ECC, not for the user data. Since ECC is maintained in the data area of SLC (2 KB), rather than the spare area of MLC (128 Bytes), ECC capability is no longer confined by the limited size of the spare area. With adaptive management, ECC capability for a page would be upgraded whenever the current ECC cannot guarantee its reliability. A quantitative analysis is conducted to explore the impacts of different settings. The experiment results show that the lifetime of SSD can be extended by 318 percent for the trace of OLTP applications with our adaptive ECC scheme.

Schemes for Extending the Lifetime of SSD

Schemes for Extending the Lifetime of SSD

Understanding performance anomalies of SSDs and their impact in enterprise application environment

SSD is known to have the erase-before-write and out-of-place update properties. When the number of invalidated pages is more than a given threshold, a process referred to as garbage collection (GC) is triggered to erase blocks after valid pages in these blocks are copied somewhere else. GC degrades both the performance and lifetime of SSD significantly because of the read-write-erase operation sequence. In this paper, we conduct intensive experiments on a 120GB Intel 320 SATA SSD and a 320GB Fusion IO ioDrive PCI-E SSD to show and analyze the following important performance issues and anomalies. The commonly accepted knowledge that the performance drops sharply as more data is being written is not always true. This is because GC efficiency, a more important factor affecting SSD performance, has not been carefully considered. It is defined as the percentage of invalid pages of a GC erased block. It is possible to avoid the performance degradation by managing the addressable LBA range. Estimating the residual lifetime of an SSD is a very challenging problem because it involves several interdependent and mutually interacting factors such as FTL, GC, wear leveling, workload characteristics, etc. We develop an analytical model to estimate the residual lifetime of a given SSD. The high random-read performance is widely accepted as one of the advantages of SSD. We will show that this is not true if the GC efficiency is low.

Post-manufacturing, 17-times acceptable raw bit error rate enhancement, dynamic codeword transition ECC scheme for highly reliable solid-state drives, SSDs

A dynamic codeword transition ECC scheme is proposed for highly reliable solid-state drives, SSDs. By monitoring the error number or the write/erase cycles, the ECC codeword dynamically increases from 512 Byte (+parity) to 1 KByte, 2 KByte, 4 KByte…32 KByte. The proposed ECC with a larger codeword decreases the failure rate after ECC. As a result, the acceptable raw bit error rate, BER, before ECC is enhanced. Assuming a NAND Flash memory which requires 8-bit correction in 512 Byte codeword ECC, a 17-times higher acceptable raw BER than the conventional fixed 512 Byte codeword ECC is realized for the mobile phone application without an interleaving. For the MP3 player, digital-still camera and high-speed memory card applications with a dual channel interleaving, 15-times higher acceptable raw BER is achieved. Finally, for the SSD application with 8 channel interleaving, 13-times higher acceptable raw BER is realized. Because the ratio of the user data to the parity bits is the same in each ECC codeword, no additional memory area is required. Note that the reliability of SSD is improved after the manufacturing without cost penalty. Compared with the conventional ECC with the fixed large 32 KByte codeword, the proposed scheme achieves a lower power consumption by introducing the “best-effort” type operation. In the proposed scheme, during the most of the lifetime of SSD, a weak ECC with a shorter codeword such as 512 Byte (+parity), 1 KByte and 2 KByte is used and 98% lower power consumption is realized. At the life-end of SSD, a strong ECC with a 32 KByte codeword is used and the highly reliable operation is achieved. The random read performance is also discussed. The random read performance is estimated by the latency. The latency is below 1.5 ms for ECC codeword up to 32 KByte. This latency is below the average latency of 15,000 rpm HDD, 2 ms.