Level-crossing Sampling Scheme Research Articles

Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices

Level crossing sampling (LCS) is a power-efficient analog-to-digital conversion scheme for spikelike signals that arise in many Internet of Things-enabled automotive and environmental monitoring applications. However, LCS scheme requires a dedicated time-to-digital converter with large dynamic range specifications. In this paper, we present a compressed LCS that exploits the signal sparsity in the time domain. At the compressed sampling stage, a continuous-time ternary encoding scheme converts the amplitude variations into a ternary timing signal that is captured in a digital random sampler. At the reconstruction stage, a low-complexity split-projection least squares (SPLSs) signal reconstruction algorithm is presented. The SPLS splits random projections and utilizes a standard least squares approach that exploits the ternary-valued amplitude distribution. The SPLS algorithm is hardware friendly, can be run in parallel, and incorporates a low-cost k-term approximation scheme for matrix inversion. The SPLS hardware is analyzed, designed, and implemented in FPGA, achieving the highest data throughput and the power efficiency compared with the prior arts. Simulations of the proposed sampler in an automotive collision warning system demonstrate that the proposed compressed LCS can be very power efficient and robust to wireless interference, while achieving an approximately eightfold data volume compression when compared with Nyquist sampling approaches.

Asynchronous analog-to-digital converter based on level-crossing sampling scheme

In this paper, a new iterative algorithm is used to convert analog signals to digital (A/D) using an asynchronous A/D converter. It is a realtime system, which encodes the amplitude information of the analog signal into a time sequence. In particular, using asynchronous systems for data conversion is an effective technique in order to reduce power consumption. The decoder should recover original signal from irregular samples. If a more intelligent reconstruction technique is used for decoding, signals with higher bandwidth can be digitized. In this work, we employ delta- and sigma-delta level-crossing sampling schemes. These asynchronous A/D converters are simple to implement and have very good performance with lower power consumption.

Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling

The recent sophistications in areas of mobile systems and sensor networks demand more and more processing resources. In order to maintain the system autonomy, energy saving is becoming one of the most difficult industrial challenges, in mobile computing. Most of efforts to achieve this goal are focused on improving the embedded systems design and the battery technology, but very few studies target to exploit the input signal time-varying nature. This paper aims to achieve power efficiency by intelligently adapting the processing activity to the input signal local characteristics. It is done by completely rethinking the processing chain, by adopting a non conventional sampling scheme and adaptive rate filtering. The proposed approach, based on the LCSS (Level Crossing Sampling Scheme) presents two filtering techniques, able to adapt their sampling rate and filter order by online analyzing the input signal variations. Indeed, the principle is to intelligently exploit the signal local characteristics--which is usually never considered--to filter only the relevant signal parts, by employing the relevant order filters. This idea leads towards a drastic gain in the computational efficiency and hence in the processing power when compared to the classical techniques.

Asynchronous level crossing analog to digital converters

We present a new class of asynchronous analog to digital converters (A-ADCs), based on an level-crossing sampling scheme of the analog signal, and an asynchronous design. Because these ADCs are not conventional, a design methodology is also presented, it takes place at a system level, then a transistor level. Its purpose is to determine the characteristics of an A-ADC given the required effective number of bits and the properties of the analog signal to convert, such as to minimize the complexity, the activity, and the power consumption. A prototype has been designed for speech applications, using the 0.18 μm CMOS technology from STMicroelectronics, and a voltage mode approach for the analog parts of the converter. Electrical simulations prove that the Figure of Merit (FoM) of this converter is increased by more than one order of magnitude compared to synchronous Nyquist ADCs. Moreover, behavioural simulations prove that the activity of the A-ADC is reduced by two orders of magnitude compared to its synchronous counterpart.