Level Converting Flip-flop Research Articles

A General Structure and High-Performance Dual-Edge Triggered Level Converting Flip–Flop Based on BiCMOS

Dual supply voltage scheme provides very effective solution to cut down power consumption in digital integrated circuits design, where level converting flip–flops (LCFF) are the key component circuits. In this paper, a new general structure and design method for dual-edge triggered LCFF based on BiCMOS is proposed, according to that PNP-PNP-DELCFF and NPN-NPN-DELCFF are designed. The experiments carried out by Hspice using TSMC 180 nm show proposed circuits have correct logic functions. Compared to counterparts, proposed PNP-PNP-DELCFF gains improvements of 6.7%, 96.0%, 86.0% and 28.5% in D-Q Delay, 50.0%, 16.0%, 12.6% and 10.8% in product of delay and power (PDP), respectively. NPN-NPN-DELCFF gains improvements of 5.1%, 93.0%, 83.2% and 26.5% in D-Q Delay, 39.7%, 7.9%, 5.0% and 3.4% in PDP, respectively. Furthermore, proposed circuits have better drive ability.

A Four-Transistor Level Converter for Dual-Voltage Low-Power Design

Power dissipation in digital circuits has become a primary concern in electronic design. With increasing usage of portable devices, there are severe restrictions being placed on the size, weight and power of batteries. In this work, we propose a design of a dual Vth feedback type four-transistor level converter (DVF4) with reduced delay and power overheads. The use of DVF4 enhances the effectiveness of a dual-voltage low-power design. The level converter can be used in a circuit with multi supply voltage system where low supply gates may feed into high supply gates resulting in lower power and higher speed than with previously published level converters. The proposed level converter is based on a feedback circuit and employs multi-Vth technique. To portray the advantages, we compare the proposed level converter with a previously published level converter for various supply voltages and observe 17.44% to 53% power savings and around 50% delay reduction over the best 32 nm CMOS design available in the literature. The impact of process variations is also examined. When used with dual VDD designs, the new level converter renders up to 61% more energy savings for benchmark circuits in comparison when level converters are not allowed. Furthermore, a level converter flip-flop combination performs better than an existing level converting flip-flop. A single-threshold alternative of the new level converter still remains effective, though over a reduced voltage range.

Low-power level converting flip-flop with a conditional clock technique in dual supply systems

Clustered voltage scaling (CVS) is an effective way to reduce power consumption in digital integrated circuits. Level-converting flip-flops are the critical elements in the CVS scheme. In this paper a single edge implicit pulse-triggered level-converting flip-flop with a conditional clock technique (CC-LCFF) is proposed and proved to be suitable for use in low-power non-critical paths with Dual-VDD. CC-LCFF conditionally blocks the clock signal when the input data does not make any transition, so the redundant transitions of internal nodes are eliminated and the total power consumption is reduced. Based on the SMIC 65nm technology, the post-layout simulation results show that the proposed CC-LCFF shows an improvement of 69.41–72.40% in power consumption and 23.36–47.73% in power-delay product (PDP) as compared with its counterparts.

A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design

SUMMARY This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-Vt and 0.84 V VDD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-Vt technology, as compared to that of the classic

Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering

Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementation of polyphase channelizer, integrating algorithmic, architectural and circuit level design techniques. At algorithm level, low complexity polyphase channelizer architecture is derived using multirate signal processing approach. To reduce the computational complexity in polyphase filters, computation sharing differential coefficient (CSDC) method is effectively used as an architectural level technique. The main idea of CSDC is to combine the strength of augmented differential coefficient method and subexpression sharing. Efficient circuit-level techniques: low power commutator implementation, dual-VDD scheme and novel level-converting flip-flop (LCFF), are also used to further reduce the power dissipation. The proposed polyphase channelizer consumes 352 mW power with throughput of 480 million samples per second (MSPS). A test chip has been fabricated in 0.18 μm CMOS technology and its functionality is verified. Chip measurement results show that the dual-VDD implementation achieves a total power saving of 2.7 X.

A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems

In this paper, we propose some soft-error-tolerant latches and flip-flops that can be used in dual-VDD systems. By utilizing local redundancy and inner feedback techniques, the latches and flip-flops can recover from soft errors caused by cosmic rays and particle strikes. The proposed flip-flop can be used as a level shifter without the problems of static leakage and redundant switching activity. Implemented in a standard 0.18- mum technology, the proposed latches and flip-flops show superior performance compared to conventional ones in terms of delay and power while keeping the soft-error-tolerant characteristic. Experimental results show that compared to the traditional built-in soft-error-tolerant D latch, the D-QN delay of the new D latch is 29.1% less than that of the traditional built-in soft-error-tolerant D latch while consuming 16.5% less power as well. The D-Q delay and power of the new flip-flop are about 47.7% and 54% less than those of the traditional high speed level-converting flip-flop, respectively. In addition, the proposed flip-flop is more robust to soft errors. The critical charge which represents the minimum charge at the D input required to cause an error of the flip-flop can be increased by more than 46.4%. The time window during which the flip-flop will be erroneous caused by single-event upsets at the D input is reduced by more than 22.2%.