Legal Placements Research Articles

Learning on the job? Addressing students’ exposure to bullying, harassment or discrimination during legal placements

ABSTRACT Law schools in the UK regularly encourage and support students to apply for vacation placement schemes on the basis that they provide valuable work experience and improve career progression prospects. There are, however, rarely any processes in place within universities to ensure equitable access to such opportunities nor systematic procedures for enabling reflection and evaluation post-placement before encouraging repeat uptake from future cohorts. In a context in which the legal profession continues to face well-documented challenges in regard to bullying, harassment and discrimination, these placements have the potential to expose students to inappropriate workplace behaviour. However, the nature of students’ experiences in this respect, and the adequacy of existing mechanisms for reporting and responding to any complaints, have not to date been the subject of sufficient scrutiny. Drawing on scoping research involving semi-structured interviews with key stakeholders, this article explores students’ potential exposure to bullying, harassment or discrimination in the particular context of mini-pupillages undertaken at the legal Bar, and calls for increased clarity across chambers, regulators and universities alike in regard to lines of communication and accountability to address this.

Blocking the Law from Within: Familyism Ideologies as Obstacles to Legal Protections for Women in El Salvador, Guatemala, Honduras, and Nicaragua.

The scholarship seeking to explain the ineffectiveness of violence against women (VAW) laws has focused on the lack of resources or will to implement these laws. Less attention has been given to how these laws are crafted and positioned in the legal hierarchy, which may undermine them from the start. This article focuses on four cases from Central America, a region where fifty-five laws to protect women from violence were passed between 1960 and 2018, yet VAW continues. It finds that the legal positioning and language of these laws prioritize family unity while undermining women's rights to protection; thus, these laws fail by design. The article identifies four legal placements that delay (El Salvador), undermine (Honduras), diminish (Nicaragua), or render abstract (Guatemala) the effectiveness of VAW laws in the context of penal and judicial codes. This work has direct policy implications and broader relevance beyond the cases examined here.

Solving modern mixed-size placement instances

Physical design of modern systems-on-chip is extremely challenging. Such digital integrated circuits often contain tens of millions of logic gates, intellectual property blocks, embedded memories and custom register-transfer level (RTL) blocks. At current and future technology nodes, their power and performance are impacted, more than ever, by the placement of their modules. However, our experiments show that traditional techniques for placement and floorplanning, and existing academic tools cannot reliably solve the placement task. To study this problem, we identify particularly difficult industrial instances and reproduce the failures of existing tools by modifying pre-existing benchmark instances. Furthermore, we propose algorithms that facilitate placement of these difficult instances. Empirically, our techniques consistently produce legal placements, and on instances where comparison is possible, reduce wirelength by 13% over Capo 9.4 and 31% over PATOMA 1.0—the pre-existing tools that most frequently produce legal placements in our experiments.

Fine Control of Local Whitespace in Placement

In modern design methodologies, a large fraction of chip area during placement is left unused by standard cells and allocated as “whitespace.” This is done for a variety of reasons including the need for subsequent buffer insertion, as a means to ensure routability, signal integrity, and low coupling capacitance between wires, and to improve yield through DFM optimizations. To this end, layout constraints often require a certain minimum fraction of whitespace in each region of the chip. Our work introduces several techniques for allocation of whitespace in global, detail, and incremental placement. Our experiments show how to efficiently improve wirelength by reallocating whitespace in legal placements at the large scale. Additionally, for the first time in the literature, we empirically demonstrate high-precision control of whitespace in designs with macros and obstacles. Our techniques consistently improve the quality of whitespace allocation of top-down as well as analytical placement methods and achieve low penalties on designs from the ISPD 2006 placement contest with minimal interconnect increase.

A Robust Mixed-Size Legalization and Detailed Placement Algorithm

Placement is one of the most important steps in the RTL-to-GDSII synthesis process as it directly defines the interconnects. The rapid increase in IC design complexity and the widespread use of intellectual-property blocks have made the so-called mixed-size placement a very important topic in recent years. The contributions of this paper include the following: 1) It proposes a flexible and robust mixed-size legalization scheme. Two constraint graphs are constructed from the global placement. Adjustments are iteratively applied to the constraint graphs until the longest paths on both graphs fall within the chip dimension. The macro coordinates are then computed by solving a linear programming (LP) formulation. The LP formulation has also been extended to handle macro spreading for routing density control. Experimental results show that our scheme can effectively legalize macros for all the global placements generated by mPL6 [1] on IBM-MSwPins. Experimental results also show that LP-based macro assignment can significantly reduce the amount of perturbation introduced during legalization compared to a greedy alternative. 2) Starting from the legalization scheme, it further proposes a three-step mixed-size detailed placement algorithm, XDP. An enhanced greedy method is used to remove the overlap between standard cells while preserving the legality of macros. Sliding-window-based cell swapping is applied in the end to further reduce the wirelength. Experiments show that, when compared with Floorist [2] with similar legalization capability, using the global placements generated by mPL6 [3], XDP is seven times faster with 6% shorter wirelength. Experiments also show that, when applied to the set of global placement results generated by APlace 2.0 [4], XDP can produce comparable wirelength to the native detailed placement of APlace 2.0 and 2% shorter wirelength compared with that with Fengshui 5.0 [5]. When applied to the set of global placements generated by mPL6, XDP is the only detailed placement that successfully produces legal placements for all 18 examples, whereas APlace and Fengshui failed for 3 and 16 of them, respectively. Furthermore, when legal placements can be compared, the wirelength produced by XDP is shorter by 8% on average compared with that with APlace. For scalability, XDP is ten times faster than APlace when applied to circuits with more than two million movable objects with comparable wirelength.

A heuristic method for solving triangle packing problem

Given a set of triangles and a rectangle container, the triangle packing problem is to determine if these triangles can be placed into the container without overlapping. Triangle packing problem is a special case of polygon packing problem and also NP-hard, so it is unlikely that an efficient and exact algorithm can be developed to solve this problem. In this paper, a new concept of rigid placement is proposed, based on which a discrete solution space called rigid solution space is constructed. Each solution in the rigid solution space can be built by continuously applying legal rigid placements one by one until all the triangles are placed into the rectangle container without overlapping. The proposed Least-Destruction-First (LDF) strategy determines which rigid placement has the privilege to go into the rectangle container. Based on this, a heuristic algorithm is proposed to solve the problem. Combining Least-Destruction-First strategy with backtracking, the corresponding backtracking algorithm is proposed. Computational results show that our proposed algorithms are efficient and robust. With slight modification, these techniques can be conveniently used for solving polygon packing problem.