LC Quadrature Voltage-controlled Oscillator Research Articles

Analytical phase noise study of a back-gate coupled colpitts quadrature VCO

This paper presents a detailed study of phase noise of an LC Quadrature Voltage-Controlled Oscillator (QVCO). This QVCO is made of coupling two identical cross-connected Colpitts oscillators as core oscillators. MOSFETs are used as varactors, the substrates of which are used for coupling the two core Colpitts oscillators. Phase noise improvement resulted from substrate coupling is not only due to elimination of noise sources (as no extra passive or active coupling devices are used) but also due to lower effective thermal noise of the substrates. To verify this, a rigorous phase noise analysis of the circuit using the Linear Time Variant (LTV) model is performed for the 1/f2 region. It indicates that the improvement is not only due to lower thermal noise of the substrate, but also a better noise modulating factor (NMF). The proposed QVCO was designed and simulated in a 0.18 ​μm RF-CMOS Technology at frequency of 5.35 ​GHz with a power consumption of 8 ​mW, tuning range of 18% and phase noise of −142.8 ​dBc/Hz at 5 ​MHz frequency offset. The presented analysis indicates a phase noise of −143 ​dBc/Hz at an offset of 5 ​MHz, which shows a good agreement with the simulation. The difference between the simulated and calculated phase noise at high frequency offsets is less than 0.2 ​dB.

An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generation

This paper presents a low-power first-order frequency synthesizer architecture suitable for high-speed on-chip clock generation. The proposed design features an architecture combining an LC quadrature voltage-controlled oscillator (VCO), two sample-and-holds, a phase interpolator, digital coarse-tuning and rotational frequency detection for fine-tuning. Similar to multiplying delay-locked loops (MDLLs), this architecture limits jitter accumulation to one reference cycle, as jitter during one reference cycle does not contribute to the next reference cycles. Also, instead of using multiplexer switches commonly employed in MDLLs, the reference clock edge is injected by phase interpolation to support higher frequencies and lower jitter. Functionality of the frequency synthesizer is validated between 8-9.5 GHz, LC VCO's range of operation. First-order dynamic of the acquisition has been analyzed and demonstrated through measurement. The output clock at 8 GHz has an integrated rms jitter of 490 fs, peak-to-peak periodic jitter of 2.06 ps and total rms jitter of 680 fs. Different components of jitter have been analyzed and separate measurements have been done to support the analysis. The reference spurs are measured to be -64.3 dB below the carrier frequency. At 8 GHz the system consumes 2.49 mW from a 1 V supply.

Low-power CMOS LC QVCO using zero-biased transistor coupling of MWCNT network-based VCO structure

This paper presents design, analysis and implementation of a 2.4GHz QVCO (Quadrature Voltage Controlled Oscillator), for low-power, low-voltage applications. Cross coupled LC VCO (Inductor–Capacitor Voltage Controlled Oscillator) topology realized using integration of a micro-scaled capacitor and a MWCNT (Multi-Wall Carbon Nano-Tube) network based inductor together with the CMOS circuits is utilized together with MOS transistors as coupling elements to realize QVCO. With the passive coupling achieved from the MOS transistors, power consumption is minimized while maintaining a small chip area. The variable capacitors and the inductors are designed using ANSYS and imported through DAC components in ADS (Advanced Design software). Accurate simulation of the QVCO is performed in the software environments and the results are provided. The measurement results show that the QVCO provides quadrature signals at 2.4GHz and achieves a phase noise of −130dBc/Hz 1MHz away from the carrier frequency. The VCO produces frequency tuning from 2.1GHz to 2.60GHz (20.83%) with a control voltage varying from 0 to 0.3V. It achieves a peak to peak voltage of 0.59V with an ultra low power consumption of 3.8mW from a 0.6V supply voltage. The output power level of the QVCO is −10dBm, with an improved quality factor of 45. The phase error of the QVCO is measured as 3.1°.

A 4.6 GHz cascade switched biasing LC–QVCO using source-body resistor

This paper presents a 4.6 GHz LC quadrature voltage-controlled oscillator (QVCO) in which the phase noise performance is improved by two methods: cascade switched biasing (CSB) technique and source-body resistor. The CSB topology can reduce the resonator loss caused by MOSFET resistance. Meanwhile, it can maintain the benefits of conventional switched biasing technique. The source-body resistors are utilized to reduce the noise contribution of the substrate related to the cross coupled MOSFETs. The proposed QVCO has been implemented in standard 0.18 μm CMOS technology. With the two methods mentioned above, it consumes 4.9 mW under 1 V voltage supply and achieves a phase noise of ?120.3 dBc/Hz at 1 MHz frequency offset from the carrier of 4.56 GHz. The figure of merit is 186.5 dBc/Hz and the tuning range is from 4.2 G to 5 GHz (17.3 %). When the QVCO operates at 0.8 V voltage supply, the power consumption is 2.88 mW and the phase noise is ?115.7 dBc/Hz at 1 MHz frequency offset from the carrier of 4.58 GHz.

An LC Quadrature VCO Using Capacitive Source Degeneration Coupling to Eliminate Bi-Modal Oscillation

A phase shift technique using capacitive source degeneration (CSD) is presented for LC quadrature voltage-controlled oscillators (QVCO), where capacitively degenerated differential pairs are used to couple the LC tanks to implement a phase-shifted transconductance and negative input resistance to compensate resonator losses, and to minimize the flicker noise contributions. The CSD technique not only introduces excess phase shift to eliminate undesired bi-modal oscillation, but inherently provides a large coupling ratio to improve quadrature phase accuracy. Compared to existing phase-shift LC-QVCOs, the proposed CSD-QVCO presents excellent phase accuracy and power efficiency. A prototype of the QVCO was fabricated in TSMC 0.18-μm CMOS technology. The measured phase noise is -120 dBc/Hz at 3-MHz offset from 5-GHz carrier, with a power consumption of 6.4 mW from a 1.2-V supply.

A LOW POWER PUSH-PUSH DIFFERENTIAL VCO USING CURRENT-REUSE CIRCUIT DESIGN TECHNIQUE

This paper presents a complementary metal-oxide- semiconductor (CMOS) difierential voltage-controlled oscillator (VCO) implemented with the push-push principle. The push-push VCO uses two frequency doublers stacked in series with an LC quadrature voltage-controlled oscillator (QVCO) to share the dc current with the QVCO for low power consumption. The proposed CMOS VCO has been implemented with the TSMC 0.18m CMOS technology, and the die area is 0:822£1:564mm 2 . At the supply voltage of 0.9V, the total power consumption is 3.15mW. The free-running frequency of VCO is tunable from 10GHz to 11.15GHz as the tuning voltage is varied from 0.0V to 1.2V. The measured phase noise at 1MHz frequency ofiset is i114:93dBc/Hz at the oscillation frequency of 9.99GHz, and the flgure of merit (FOM) of the proposed VCO is i190:0dBc/Hz.

A low power, low phase noise, square wave LC quadrature VCO and its comprehensive analysis for ISM band

This paper presents a phase-noise reduction technique for voltage-controlled oscillators (VCOs) using a harmonic tuned (HT) LC tank. The phase-noise suppression is achieved through almost rectangular-shaped VCO oscillating signal which effectively maximizes oscillating signal slope at zero crossing points resulting in-phase-noise degradation. In addition, by shortening down converted noise power around oscillating signal second harmonic, more phase-noise suppression has been achieved. A comprehensive analysis for frequency and amplitude deviations as high as 20% for third harmonic and its effect on output phase-noise suppression has been discussed. In the followings, a comprehensive analysis on time-variant theory of phase noise where a more simplistic time-invariant approach fails to explain numerical simulation results even at the qualitative level has been exposed. General closed-form formulas are derived for the phase noise generated by LC tanks losses and MOS transistors noisy current. It is also shown that by using third harmonic tank on VCO and steering coupling and coupled section current sources by quadrature signals, total phase-noise improvement will be as high as 9 dB compared to conventional structures. Designed harmonic tuned LC Quadrature VCO has been fabricated using 0.18 um 1P6M CMOS technology operating at 1.8 V for frequency band of 2.4–2.6 GHz with achieved phase noise of −136 dBc/Hz at frequency offset of 3 MHz. Total current drawn by VCO is 3.9 mA making the power consumption as low as 7 mW with the silicon area of 500 um × 500 um. Implemented HT VCO figure-of-merit (FOM) is −186 dB making the implemented VCO superior compared to the recently published VCOs. An extensive spectreRF simulation covering a wide range of operating conditions has been used to verify the theoretical analyses.

A new robust capacitively coupled second harmonic quadrature LC oscillator

A study of some reported superharmonic LC quadrature voltage-controlled oscillator (LC-QVCO) is performed in which it is shown that robustness of the quadrature oscillation varies depending on the coupling configuration. Next, a new superharmonic LC-QVCO is proposed in which the common source node in either of two identical cross-connected LC-VCOs is coupled via a capacitor to the node common between the two varactors in the LC-tank of the other LC-VCO. As a result of connecting common mode nodes, the currents flowing through the two coupling capacitors are comprised of only the even harmonics. In the proposed coupling configuration there exists a closed loop through which the second harmonic signals circulate. A qualitative argument is presented to justify the robustness of the quadrature nature of the proposed QVCO by applying the Barkhausen phase criterion to the second harmonic signals in the loop. Since the coupling devices are only two capacitors, no extra noise sources and power consumption are added to the core VCOs. A Monte-Carlo simulation showed that the phase error of the proposed QVCO caused by device mismatches is no more than 1°. Also, generalizing this method to several numbers of VCOs in a loop, multiphase signals can be generated. The proposed circuits were designed using a 0.18-μm RF CMOS technology and simulation results are presented.

New capacitive coupled superharmonic quadrature LC-VCO

A study of some reported LC quadrature voltagecontrolled oscillators (LC-QVCO) is performed in which it is shown that robustness of the quadrature oscillation varies depending on the coupling configuration. Next, a new superharmonic LC-QVCO is proposed in which the common source node in either of two identical crossconnected LC-VCOs is coupled via a capacitor to the node common between the two varactors in the LC tank of the other LC-VCO. In the proposed coupling configuration there exists a closed loop through which the second harmonic signals circulate. A qualitative argument is presented to justify the robustness of the quadrature nature of the proposed QVCO by applying the Barkhausen phase criterion to the second harmonic signals in the loop. Since the coupling devices are only two capacitors, no extra noise sources and power consumption are added to the core VCOs. A Monte Carlo simulation showed that the phase error of the proposed QVCO is no more than 1o. Also, generalizing this method to several numbers of VCOs in a loop, multiphase signals can be generated. The proposed circuits were designed using a 0.18-µm RF CMOS technology and simulation results are presented.

A new low-phase noise direct-coupled CMOS LC-QVCO

A new LC quadrature voltage-controlled oscillator (LC-QVCO), made with direct coupling of two CMOS LC-VCOs, is presented. In the proposed circuit two identical cross-connected LC-VCOs are coupled together by directly connecting the bulk of the cross-connected transistors of one VCO to the bulk of the MOS varactors of the other VCO in such a way no extra devices are needed for coupling. Thus, no extra noise sources and power consumption are added to the core VCOs and results in high performance of QVCO. A Linear analysis of the circuit and the result of simulation in a 0.18µm CMOS technology are presented. The same proposed coupling scheme can be used for multiphase signal generation as well. Simulation shows the proposed QVCO can operate with supply voltage as low as 0.5V.

Analysis of resonator phase shift for two series LC quadrature VCOs

Based on the investigation of resonator phase shift, an analytical framework to compare the phase noise between two series LC quadrature voltage-controlled oscillators (QVCOs) is presented. The bottom-series QVCO is analytically demonstrated to have lower phase noise than the top-series QVCO. Simulation data show good agreement with the presented analysis.

Comparative study of gigahertz CMOS LC quadrature voltage-controlled oscillators with relevance to phase noise

This review paper presents a comparative study of published integrated submicron CMOS quadrature voltage-controlled oscillator designs, based on LC resonator tanks operating at gigahertz frequencie...

Sinusoidal-switched serial-coupled CMOS LC quadrature VCO

A new topology to design low-phase-noise low-power quadrature voltage-controlled-oscillator (QVCO) is proposed. The proposed topology is based on using a dynamic transistor biasing scheme in a typical voltage-controlled-oscillator (VCO). This method modifies the equivalent impulse-sensitivity-function (ISF) of oscillator to reduce the oscillator sensitivity to noise sources and as a result reducing the oscillator phase noise. A 1.8GHz, 1.8v designed QVCO with 0.18u CMOS technology based on the proposed topology shows a phase noise of -134dBc/Hz at 1MHz offset frequency from the carrier.

A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector

This paper presents a 10-Gb/s clock and data recovery (CDR) and demultiplexer IC in a 0.13-mum CMOS process. The CDR uses a new quarter-rate linear phase detector, a new data recovery circuit, and a four-phase 2.5-GHz LC quadrature voltage-controlled oscillator for both wide phase error pulses and low power consumption. The chip consumes 100 mA from a 1.2-V core supply and 205 mA from a 2.5-V I/O supply including 18 preamplifiers and low voltage differential signal (LVDS) drivers. When 9.95328-Gb/s 231-1 pseudorandom binary sequence is used, the measured bit-error rate is better than 10-15 and the jitter tolerance is 0.5UIpp, which exceeds the SONET OC-192 standard. The jitter of the recovered clock is 2.1 psrms at a 155.52MHz monitoring clock pin. Multiple bit rates are supported from 9.4 Gb/s to 11.3 Gb/s

Low Power Low Phase Noise LC Quadrature VCO Topology

A simple low power low phase noise LC QVCO (Quadrature Voltage Controlled Oscillator) topology is proposed. The topology minimizes phase noise by eliminating the contributions from the tail current source and coupling transistors. With no more than 3.36 mW power consumption from a 1.2 V power supply, the VCO achieves -124dBc/Hz phase noise performance at 1 MHz offset from the 2.85 GHz carrier frequency.

Low-phase-noise LC quadrature VCO using coupled tank resonators in a ring structure

The concept of coupled resonators is employed in a ring VCO structure to reduce the phase noise. This architecture allows the design of low-phase-noise voltage controlled oscillators (VCOs) using integrated low-Q inductors. Quadrature differential outputs are also realized in this design. Two monolithic LC tanks are coupled together to implement a transimpedance resonator with an effective Q close to twice that of a single tank. In addition, the coupled tank's transimpedance resonator provides 90/spl deg/ phase shift. Four such stages are cascaded in a ring structure to provide I-Q differential outputs, and to further reduce the phase noise. A prototype of the VCO is built in a 0.35-/spl mu/m CMOS technology. The measured phase noise is -122 dBc/Hz at 600-kHz offset from 1.93 GHz. The VCO draws 9.2 mA from a 3-V supply, and occupies a chip area of 1.1/spl times/1.1 mm/sup 2/.