Lateral Asymmetric Channel MOSFETs Research Articles

Analysis and modeling of flicker noise in lateral asymmetric channel MOSFETs

In this paper, flicker noise behavior of lateral non-uniformly doped MOSFET is studied using impedance field method. Our study shows that Klaassen Prins (KP) method, which forms the basis of noise model in MOSFETs, underestimates flicker noise in such devices. The same KP method overestimates thermal noise by 2–3 orders of magnitude in similar devices as demonstrated in Roy et al. (2007). This apparent discrepancy between thermal and flicker noise behavior lies in origin of these noises, which leads to opposite trend of local noise power spectral density vs doping. We have modeled the physics behind such behavior, which also explain the trends observed in the measurements (Agarwal et al., 2015).

Evaluation of the Impact of Layout on Device and Analog Circuit Performance With Lateral Asymmetric Channel MOSFETs

Lateral asymmetric channel (LAC) or single halo devices have been reported to exhibit excellent short channel behavior in the sub-100-nm regime. In this paper, we have quantified the performance degradation in LAC devices due to fingered layouts. Our mixed-mode two-dimensional simulation results show that though the fingered layout of the device limits the performance of these MOSFETs, they still show superior performance over the conventional devices in the sub-100-nm channel length regime. We also present the simulation results of a two-stage operational amplifier with LAC and conventional devices using a 0.13-/spl mu/m technology with the help of look-up table simulations. Our results show that for the given design specifications, an OPAMP layout with conventional devices occupies 18% more chip area compared to the LAC device.

Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance

In this paper, we have systematically investigated the effect of scaling on analog performance parameters in lateral asymmetric channel (LAC) MOSFETs and compared their performance with conventional (CON) MOSFETs for mixed-signal applications. Our results show that, in LAC MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/I/sub D/ etc.) down to the 70-nm technology node, in addition to an improvement in drive current and other parameters over a wide range of channel lengths. A systematic comparison on the performance of amplifiers and CMOS inverters with CON and LAC MOSFETs is also performed. The tradeoff between power dissipation and device performance is explored with detailed circuit simulations for both CON and LAC MOSFETs.

A study of hot-carrier induced interface-trap profiles in lateral asymmetric channel MOSFETs using a novel charge pumping technique

The spatial distribution of interface traps in hot-carrier stressed lateral asymmetric channel (LAC) and conventional (CON) MOSFETs have been determined using a novel charge pumping technique. Detailed post-stress interface characterization shows reduced interface-trap buildup and lesser drain current degradation in LAC MOSFETs compared to the CON device, for stressing at different times and drain biases and for all channel lengths down to 100 nm. The interface-trap profile parameters (peak magnitude and spread) have been correlated to drain current degradation as function of stress drain bias and time. It is shown that with increased stress drain bias and time, both the peak and spread of the interface-trap profiles increase, but at different rates. While the peaks evolve identically for CON and LAC MOSFETs, the spreads do not, which is shown to affect the rate of the resulting transconductance degradation differently. Device simulations show a lower peak lateral electric field in LAC MOSFETs compared to CON devices, which is responsible for the observed reduction in hot-carrier degradation in such devices.

A study of 100 nm channel length asymmetric channel MOSFET by using charge pumping

Lateral Asymmetric Channel (LAC) MOSFETs with channel lengths down to 0.1 μm have been fabricated and characterized for their electrical performance. Using charge pumping, we show, for the first time, channel V T profiles obtained experimentally, demonstrating realization of asymmetric channel MOSFETs down to 0.1 μm channel lengths. Our detailed experimental characterizations show improved performance for LAC MOSFETs over conventional MOSFETs, in addition to excellent hot-carrier reliability. Based on 2-D device simulation results, we attribute the improved hot-carrier reliability in LAC MOSFETs to the reduced peak lateral electric field in the channel.