Large Memory Systems Research Articles

Nonlinear noise spectrum measurement using a probability-maintained noise power ratio method

Nonlinear distortion (noise) limits many communication systems, demanding a means of estimating system performance via device nonlinear characteristics. The noise power ratio (NPR) method which was proposed in 1971 solves this problem for systems with Gaussian stimuli or with special nonlinearity, but practical and accurate methods for many communication systems with non-Gaussian stimuli are rare. Here we propose a probability-maintained (PM) NPR method to accurately measure the spectrum of nonlinear noise via a spectrum analyzer in non-specific systems, including systems with non-Gaussian stimuli. Using an equivalent additive noise model in which the spectrum of equivalent nonlinear noise is the measurement result of PM NPRs, nonlinear system performance could be estimated with an error of 0.5 dB. Further, we find that zero-mean Chi-square noise, instead of Gaussian noise, should be selected for large memory and low-order nonlinear systems. Our method is verified in seven different scenarios with various nonlinear mechanisms and communication applications.

Supporting Superpages and Lightweight Page Migration in Hybrid Memory Systems

Superpages have long been used to mitigate address translation overhead in large-memory systems. However, superpages often preclude lightweight page migration, which is crucial for performance and energy efficiency in hybrid memory systems composed of DRAM and non-volatile memory (NVM). In this article, we propose a novel memory management mechanism called Rainbow to bridge this fundamental conflict between superpages and lightweight page migration. Rainbow manages NVM at the superpage granularity, and uses DRAM to cache frequently accessed (hot) small pages within each superpage. Correspondingly, Rainbow utilizes split TLBs to support different page sizes. By introducing an efficient hot page identification mechanism and a novel NVM-to-DRAM address remapping mechanism, Rainbow supports lightweight page migration without splintering superpages. Experiment results show that Rainbow can significantly reduce applications’ TLB misses by 99.9%, and improve application performance (in terms of IPC) by up to 2.9× (45.3% on average) when compared to a state-of-the-art memory migration policy without a superpage support.

Code generation for efficient query processing in managed runtimes

In this paper we examine opportunities arising from the convergence of two trends in data management: in-memory database systems (imdbs), which have received renewed attention following the availability of affordable, very large main memory systems; and language-integrated query, which transparently integrates database queries with programming languages (thus addressing the famous 'impedance mismatch' problem). Language-integrated query not only gives application developers a more convenient way to query external data sources like imdbs, but also to use the same querying language to query an application's in-memory collections. The latter offers further transparency to developers as the query language and all data is represented in the data model of the host programming language. However, compared to imdbs, this additional freedom comes at a higher cost for query evaluation. Our vision is to improve in-memory query processing of application objects by introducing database technologies to managed runtimes. We focus on querying and we leverage query compilation to improve query processing on application objects. We explore different query compilation strategies and study how they improve the performance of query processing over application data. We take C# as the host programming language as it supports language-integrated query through the linq framework. Our techniques deliver significant performance improvements over the default linq implementation. Our work makes important first steps towards a future where data processing applications will commonly run on machines that can store their entire datasets in-memory, and will be written in a single programming language employing language-integrated query and imdb-inspired runtimes to provide transparent and highly efficient querying.

Nano-Crossbar Memories Comprising Parallel/Serial Complementary Memristive Switches

This work explores anti-serial (anti-parallel) memristive switches—ASMs (APMs)—as potential cross-point elements in nano-crossbar resistive random access memory arrays. The memory operation principles for both device combinations are shown in detail. The effectiveness of these memristive structures to the solution of the parasitic conducting (current sneak paths) problem is presented via an analytical approach which is based on the basic setup of resistive crossbar memories. Simulation results of crossbars of up to 4,096 elements, arranged in quadratic configurations, are conducted. The provided results supplement this comprehensive analysis of APMs and ASMs, outlining their overall performance characteristics and commenting on their applicability to the practical realization of large crossbar memory systems. Finally, a special array topology is applied to an ASM-based crossbar memory. Its performance is compared to the performance of the pure ASM-based memory. The conducted simulations reveal significantly improved read-out voltage margins which further contribute to addressing the parasitic current paths which prevent the reliable operation of memristive crossbar circuit topologies.

Special issue for data intensive eScience

Data-intensive science is enabled by the data deluge and has been called the “fourth paradigm” of scientific discovery. New fields are being born, such as drug discovery based on large scale study of correlations in published papers and climate implications from data on the accelerating pace of changes in previously quiescent ice sheets. Astronomy and the search for fundamental particles at the Large Hadron Collider drive mainstream aspects of data-intensive science with many petabytes of data derived from large advanced instruments. Medical imagery and genomics have as much data but from a slew of distributed instruments. It is projected that there will be 24 billion devices on the Internet by 2020. Most of this “Internet of Things” will be small sensors that produce streams of information which will be processed and integrated with other streams and turned into knowledge. The deluge and its impact are pervasive. In synergy with moving to a data-driven world, we are also in the midst of an evolution in the compute landscape of hardware systems. We now live in the world of massive multi-core and GPU processing systems, very large main memory systems, fast networking components, fast solid state drive, and large data centers that consume massive amounts of energy. Computing paradigm is changing and suggesting new programming models, new data structures and more attention to fault tolerance while enabling much easier access to computing. It is clear that many aspects of how we have dealt with data processing have to change in this new world.

MR3-SMP: A symmetric tridiagonal eigensolver for multi-core architectures

The computation of eigenvalues and eigenvectors of symmetric tridiagonal matrices arises frequently in applications; often as one of the steps in the solution of Hermitian and symmetric eigenproblems. While several accurate and efficient methods for the tridiagonal eigenproblem exist, their corresponding implementations usually target uni-processors or large distributed memory systems. Our new eigensolver MR^3-SMP is instead specifically designed for multi-core and many-core general purpose processors, which today have effectively replaced uni-processors. We show that in most cases MR^3-SMP is faster and achieves better speedups than state-of-the-art eigensolvers for uni-processors and distributed-memory systems.

Long-Time Data Storage: Relevant Time Scales

Dynamic processes relevant for long-time storage of information about human kind are discussed, ranging from biological and geological processes to the lifecycle of stars and the expansion of the universe. Major results are that life will end ultimately and the remaining time that the earth is habitable for complex life is about half a billion years. A system retrieved within the next million years will be read by beings very closely related to Homo sapiens. During this time the surface of the earth will change making it risky to place a small number of large memory systems on earth; the option to place it on the moon might be more favorable. For much longer timescales both options do not seem feasible because of geological processes on the earth and the flux of small meteorites to the moon.

Coarse-grained molecular dynamics studies of cluster-bombarded benzene crystals

As high-energy cluster projectile beams become standard analysis probes for SIMS, simulating larger crystals is now a requirement for the modeling community due to the large sputtering yields. As crystals get larger, computer resources become a limitation. Even though computer technology has evolved to include large memory systems and fast processors, there are still issues with having sufficient resources to run a calculation. This manuscript reports a method of studying a full crystal of benzene after impact with a 500 eV C 60 projectile using a coarse-grained model. The potentials developed for this model incorporate the C H bond of benzene into a single coarse-grained bead. This coarse-grained method has several advantages over atomistic models—the amount of time to perform these calculations has been drastically reduced and the potentials for this sample are pair-wise additive potentials. A discussion is made as to how these results compare to those obtained with fully atomistic calculations using the AIREBO potential.

대용량 주기억장치 시스템에서 효율적인 연관 규칙 탐사 알고리즘

This paper propose an efficient algorithm for mining association rules in the large main memory systems. To do this, the paper attempts firstly to extend the conventional algorithms such as DHP and Partition in order to be compatible to the large main memory systems and proposes secondly an algorithm to improve Partition algorithm by applying the techniques of the hash table and the bit map. The proposed algorithm is compared to the extended DHP within the experimental environments and the results show up to 65% performance improvement in comparison to the expanded DHP.

Algorithm 799: revolve

In its basic form, the reverse mode of computational differentiation yields the gradient of a scalar-valued function at a cost that is a small multiple of the computational work needed to evaluate the function itself. However, the corresponding memory requirement is proportional to the run-time of the evaluation program. Therefore, the practical applicability of the reverse mode in its original formulation is limited despite the availability of ever larger memory systems. This observation leads to the development of checkpointing schedules to reduce the storage requirements. This article presents the function revolve, which generates checkpointing schedules that are provably optimal with regard to a primary and a secondary criterion. This routine is intended to be used as an explicit “controller” for running a time-dependent applications program.

A fram tera-byte memory system—you can't get there from here! (or can you?)

A user's perspective is presented in a tera-byte, non-volatile, memory system trade study. The study compares physical and performance characteristics of several technologies using a basic architecture. The purposes of the trade study are: (1) to assess implementing a 1TB system within five years and (2) to assess several technologies for use in the system. For volatile memory, the requirements of battery back-up for system non-volatility are established. The system architecture is based on potential military, aerospace, and commercial applications of large capacity memory systems and their respective requirements.

Effect of real-time weighted integration system for rapid calculation of functional images in clinical positron emission tomography

A system has been developed to rapidly calculate images of parametric rate constants, without acquiring dynamic frame data for clinical positron emission tomography (PET). This method is based on the weighted-integration algorithms for the two- and three-compartment models, and hardware developments (real-time operation and a large cache memory system) in a PET scanner, Headtome-IV, which enables the acquisition of multiple sinograms with independent weight integration functions. Following the administration of the radiotracer, the scan is initiated to collect multiple time-weighted, integrated sinograms with three different weight functions. These sinograms are reconstructed and the images, with the arterial blood data, are inserted into the operational equations to provide parametric rate constant images. The implementation of this method has been checked in H(2)(15 )O and (18)F-fluorophenylalanine ((18)FPhe) studies based on a two-compartment model, and in a (18)F-fluorodeoxyglucose ((18)FDG) study based on the three-compartment model. A volunteer study, completed for each compound, yielded results consistent with those produced by existing nonlinear fitting methods. Thus, this system has been developed capable of generating rapidly quantitative, physiological images, without dynamic data acquisition, which will be of great advantage to PET in the clinical environment. This system would also be of great advantage in the new generation high-resolution PET tomography, which acquire data in a 3-D, septaless mode.

Parallel algorithms for solving large linear systems

The solution of linear systems continues to play an important role in scientific computing. The problems to be solved often are of very large size, so that solving them requires large computer resources. To solve these problems, at least supercomputers with large shared memory or massive parallel computer systems with distributed memory are needed. This paper gives a survey of research on parallel implementation of various direct methods to solve dense linear systems. In particular are considered: Gaussian elimination, Gauss-Jordan elimination and a variant due to Huard (1979), and an algorithm due to Enright (1978), designed in relation to solving (stiff) ODEs, such that stepsize and other method parameters can easily be varied. Some theoretical results are mentioned, including a new result on error analysis of Huard's algorithm. Moreover, practical considerations and results of experiments on supercomputers and on a distributed-memory computer system are presented.

Associative memory in a network of ‘spiking’ neurons

The Hopfield network provides a simple model of an associative memory in a neuronal structure. It is, however, based on highly artificial assumptions, especially the use of formal two-state neurons or graded-response neurons. The authors address the question of what happens if formal neurons are replaced by a model of ‘spiking’ neurons. They do so in two steps. First, they show how to include refractoriness and noise into a simple threshold model of neuronal spiking. The spike trains resulting from such a model reproduce the distribution of interspike intervals and gain functions found in real neurons. In a second step they connect the model neurons so as to form a large associative memory system. The spike transmission is described by a synaptic kernel which includes axonal delays, ‘Hebbian’ synaptic efficacies, and a realistic postsynaptic response. The collective behaviour of the system is predicted by a set of dynamical equations which are exact in the limit of a large and fully connected network that...

Associative memory in a network of ‘spiking’ neurons

The Hopfield network provides a simple model of an associative memory in a neuronal structure. It is, however, based on highly artificial assumptions, especially the use of formal two-state neurons or graded-response neurons. The authors address the question of what happens if formal neurons are replaced by a model of ‘spiking’ neurons. They do so in two steps. First, they show how to include refractoriness and noise into a simple threshold model of neuronal spiking. The spike trains resulting from such a model reproduce the distribution of interspike intervals and gain functions found in real neurons. In a second step they connect the model neurons so as to form a large associative memory system. The spike transmission is described by a synaptic kernel which includes axonal delays, ‘Hebbian’ synaptic efficacies, and a realistic postsynaptic response. The collective behaviour of the system is predicted by a set of dynamical equations which are exact in the limit of a large and fully connected network that has to store a finite number of patterns. The authors show that in a stationary retrieval state the statistics of the spiking dynamics is completely wiped out and the system reduces to a network of graded-response neurons. In the case of an oscillatory retrieval state, however, the spiking noise and the internal time constants of the neurons become important and determine the behaviour of the system.

A fast exact least mean square adaptive algorithm

A general block formulation of the least-mean-square (LMS) algorithm for adaptive filtering is presented. This formulation has an exact equivalence with the original LMS algorithm; hence it retains its convergence properties, while allowing a reduction in arithmetic complexity, even for very small block lengths. Working with small block lengths is interesting from an implementation point of view (large blocks result in large memory and large system delay) and allows a significant reduction in the number of operations. Tradeoffs between a number of operations and a convergence rate are obtainable by applying certain approximations to a matrix involved in the algorithm. Hence, the usual block LMS appears as a special case, which explains its convergence behavior according to the type of input signal (correlated or uncorrelated). >

MVM: A GaAs microprocessor for critical real-time applications

The MVM processor is a 16-bit GaAs microprocessor designed for speed-demanding signal processing and controls environments. A number of design trade-offs were made in order to tune up the design for the target workload model (a set of Purdue University benchmarks for signal processing and control). A major goal was to exploit the inherent speed of the technology while coping with problems such as its very limited density of integration, high off-chip speed penalty, and the high cost of implementing large GaAs memory systems. To that end several new and innovative techniques such as vertical migration, direct compilation to microcode, and multiple ALU design, have been exploited. The pipeline hazard control is moved to the compilation phase. Program memory (microcode) and data memory are external to the chip. The memory is two-way interleaved and can be implemented not only in GaAs but in advanced silicon ECL and CMOS technologies with access time under 20 ns. The design takes 21 K transistors, including a seven window dual port register file, and the data path. The system is clocked at 400 MHz. The peak throughput of this uniprocessoy system is 133 MIPS.

Content addressability: an exercise in the semantic matching of hardware and software design

This paper considers content addressability and discusses its potential impact on software engineering in the context of its affinity to, and thus efficient implementation of, common abstract data types. More generally, the authors present an approach to language design based on the abstracted characteristics of the implementing hardware. Based on the perceived needs of common data types, a prototype MOS VLSI content addressable memory component is designed together with enhancements leading to large fault-tolerant memory systems. A novel computer architecture is introduced to include this component and to provide an example target machine. The specification of a high level programming language, using a tractable set of extensions to conventional language syntax, then completes the programming environment.

A 4-Kbit associative memory LSI

A 4-Kb (128 words/spl times/32 bits) CMOS associative-memory large-scale integration (LSI) is described. This LSI has all the functions necessary to achieve a self-operative high-speed data search system. Garbage data collection capabilities have been built into the chip in order to develop self-operative systems. The chip's paralleled and pipelined multiple-response resolver makes high-speed, high-throughput data retrieval possible. On-chip extension capabilities for word length and count simplify attainment of a large associative memory system. A newly developed cell circuit allows for simultaneous parallel-writing operation for multiple words. This LSI, which is fabricated using 3-/spl mu/m and double-aluminium-layer CMOS process technology, has a 140-ns measured minimum cycle time and 250-mW measured power dissipation at 5-MHz operation.

Lifetime analyses of error-control coded semiconductor RAM systems

The paper is concerned with developing quantitative results on the lifetime of coded random-access semiconductor memory systems. Although individual RAM chips are highly reliable, when large numbers of chips are combined to form a large memory system, the reliability may not be sufficiently high for the given application. In this case, error-correction coding is used to improve the reliability and hence the lifetime of the system. Formulas are developed which will enable the system designer to calculate the improvement in lifetime (over an uncoded system) for any particular coding scheme and size of memory. This will enable the designer to see if a particular memory system gives the required reliability, in terms of hours of lifetime, for the particular application. In addition, the designer will be able to calculate the percentage of identical systems that will, on average, last a given length of time.