Large SRAM Research Articles

Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes

Graphene-based interconnects are considered promising replacements for traditional copper (Cu) interconnect due to their great electric properties. In this article, an interconnect-memory co- design framework is developed to efficiently optimize various graphene-based interconnect technologies. Four interconnect materials and heterogeneous design schemes are benchmarked against their traditional Cu counterparts to optimize large cache-level SRAM performance in terms of delay and energy per access, energy-delay product (EDP), and energy-delay-area product (EDAP). A large design space exploration is performed based on realistic subarray design and device technology. Various interconnect- and array-level design parameters are studied to quantify the true potential of graphene-based wires for optimal memory performance.

A 250-mW 5.4G-Rendered-Pixel/s Realistic Refocusing Processor for High-Performance Five-Camera Mobile Devices

Digital refocusing in multi-camera mobile devices is becoming crucial. Realistic refocusing, which is a subset of digital refocusing, provides physically-correct quality; however, its intense computational complexity results in low processing speed and restricts its applicability. Moreover, its complex computation flow requires substantial DRAM bandwidth and a large SRAM area, making it more challenging to implement in hardware. In this paper, we present a high-performance refocusing processor based on a hardware-oriented realistic refocusing algorithm. The proposed compact computation flow saves 92% of the DRAM bandwidth and 32% of the SRAM area without noticeable quality degradation. To support high-performance refocusing, we develop highly paralleled engines for view rendering. They deliver 5.4G rendered-pixel/sec throughput. The hardware accelerator improves the processing speed by 100× to 350× that of the original refocusing algorithm running on a general purpose processor. The chip is fabricated with 40nm CMOS technology and comprises 271KB of SRAM and 2.3M logic gates. The chip processes Full-HD light fields up to 40 frames per second under 250mW power consumption.

Enabling In-Memory Computations in Non-Volatile SRAM Designs

The rapid growth in development of neural networks has necessitated the requirement of large capacity on-chip SRAM’s for Machine Learning accelerators. This has resulted in SRAM’s occupying significant portion of the die area. Furthermore, due to increased short channel effects in advanced CMOS technology nodes, the Vt of the transistors are increased to reduce the leakage power effectively. Vt increase results in direct increase in V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> (minimum operating voltage) of the device. The conventional 6T SRAM with the use of RRAM(R) to store the bitcell storage node values and PTM(S) as a selector device (6T-2R-2S) can help in decoupling V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> and Vt requirement with minimum area overhead. Functionalities of 6T-2R-2S bitcell are investigated to present a 2T-2R-2S mode and SRAM-RRAM hybrid mode of operation, further utilized in performing Compute in Memory(CIM). The above functionalities can be presented in a 8T2R bitcell, that makes use of transistor in place of PTM. 2T-2R-2S/2T-2R mode is a fully non-differential mode of operation, leveraging only the NVM portion of the bitcell. Furthermore, SRAM-RRAM hybrid mode is proposed making use of the SRAM read port transistors to perform read operation of the data stored on the RRAM, during standby mode. The architecture study of set-associative cache made of 6T-2R-2S array is also presented. The 2T-2R-2S/2T-2R mode coupled with SRAM-only mode can be efficiently used to perform CIM for dot product and XNOR computation with co-locating the weights and activations stored onto the same bitcell. System level study highlighting energy efficiency and speedup along with the proposed CIM architecture’s analysis on CIFAR-10 dataset is presented. Design sensitivity analysis with respect to PTM and RRAM parameters is discussed for both the bitcells.

Aging-Resilient SRAM-based True Random Number Generator for Lightweight Devices

A random number generator (RNG) is an important building block for cryptographic operations primarily to generate random nonces and secret keys. The power-up value of an SRAM array has been widely accepted as an entropy source for generating random numbers. However, only a few cells of the SRAM are truly random upon repeated power-ups; the vast majority of cells display a distinct bias from manufacturing process variations. Consequently, a relatively large SRAM array is required to obtain sufficient entropy for generating random numbers. Earlier research has proposed the use of controlled device aging at pre-deployment stage to enhance the initial entropy of an SRAM array. However, aging in the field can adversely affect the entropy and degrade randomness; we show here that any initial aging to increase SRAM entropy can even be counterproductive. Instead, we propose an SRAM-based random number generation approach, which continually manipulates device aging during operation to constantly maximize entropy for the entire deployment period. The key idea is to continually stress the SRAM cells in their power-up states at regular intervals. This helps counteract the aging caused by the random memory states that occur during operation. Silicon results are presented to validate our proposed approach.

Design and Analysis of Low Power SRAM using CMOS Technology

The power consumption in commercial processors and application specific integrated circuits increases with decreasing technology nodes. Power saving techniques have become a first class design point for current and future VLSI systems. These systems employ large on-chip SRAM memories. Reducing memory leakage power while maintaining data integrity is a key criterion for modern day systems. Unfortunately, state of the art techniques like power-gating can only be applied to logic as these would destroy the contents of the memory if applied to a SRAM system. Fortunately, previous works have noted large temporal and spatial locality for data patterns in commerical processors as well as application specific ICs that work on images, audio and video data. This paper presents a novel column based Energy Compression technique that saves SRAM power by selectively turning off cells based on a data pattern. This technique is applied to study the power savings in application specific inegrated circuit SRAM memories and can also be applied for commercial processors. The paper also evaluates the effects of processing images before storage and data cluster patterns for optimizing power savings..

FISE: A Forwarding Table Structure for Enterprise Networks

With increasing demands for more flexible services, the routing policies in enterprise networks become much richer. This has placed a heavy burden to the current router forwarding plane in support of the increasing number of policies, primarily due to the limited capacity in TCAM, which further hinders the development of new network services and applications. The scalable forwarding table structures for enterprise networks have therefore attracted numerous attentions from both academia and industry. To tackle this challenge, in this paper we present the design and implementation of a new forwarding table structure. It separates the functions of TCAM and SRAM, and maximally utilizes the large and flexible SRAM. A set of schemes are progressively designed, to compress storage of forwarding rules, and maintain correctness and achieve line-card speeds of packet forwarding. We further design an incremental update algorithm that allows less access to memory. The proposed scheme is validated and evaluated through a realistic implementation on a commercial router using real datasets. Our proposal can be easily implemented in the existing devices. The evaluation results show that the performance of forwarding tables under the proposed scheme is promising.

Physically Unclonable Functions Using Foundry SRAM Cells

This paper describes a low voltage physically unclonable function (PUF) implemented with SRAM circuits. The approach allows the use of foundry cells, which are used in this paper, and requires very minor modifications to standard SRAM arrays. The PUF functionality is designed into large 1M-bit SRAM arrays fabricated on a 55-nm process using the foundry supplied SRAM cell layouts. The low variability foundry process produces good PUF results, demonstrating that the approach should also be good on conventional processes, since greater mismatch should positively impact PUF performance as measured by code word stability. The impact of process corners is also experimentally determined. Unstable bits, which we attribute to random telegraph noise is shown to be at manageable levels. We describe the circuit operation, statistical behavior, and suggest helper data functions that allow operation without error correction. This is important since error correction necessarily allows some leakage of the underlying secret codes.

SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability

This paper describes a novel approach to a true random number generator (TRNG) using SRAM circuits. The principles of operation are described in the context of past work on integrated circuit TRNGs. The required modifications to standard SRAM arrays are minor and have little impact on the area. Experimental results from large 1-Mbit SRAM arrays fabricated on a 55-nm process using the foundry supplied SRAM cell layouts show good results. Simple helper functions, suitable for very small hardware implementation, allow improvement, including the ability for the resulting binary strings to pass all of the National Institute of Standards randomness tests. We describe the circuits, their principle of operation and statistical behavior, as well as the underlying physical mechanisms providing the entropy.

Recoil-Ion-Induced Single Event Upsets in Nanometer CMOS SRAM Under Low-Energy Proton Radiation

Low-energy (<10 MeV) proton-induced single event upsets (SEUs) were investigated through proton and heavy ion experiments on a 65 nm CMOS bulk SRAM. It is unlikely that 2-10 MeV proton direct ionization can induce SEUs in the 65 nm SRAM and the observed single-bit upsets (SBUs) and multiple cell upsets (MCUs) are mainly induced by the ionization from the recoil ions. The MCUs induced by low-energy protons in our 65 nm SRAM can be corrected by the error correction codes (ECC) because they usually occur along the SRAM bit line. The Geant4 simulations revealed that the SEU cross-section may show two different trends for 2-10 MeV protons depending on the critical charge for triggering a SEU. With the increase of proton energy, SEUs in small critical charge SRAM tend to decrease while SEUs in large critical charge SRAM tend to increase. Further, the Geant4 simulations demonstrated that the SEUs induced by recoil oxygen are more than those induced by recoil silicon and SEUs induced by recoil ions from elastic collisions dominate in our 65 nm CMOS SRAM under 2-10 MeV proton radiation.

An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies

Increased process variability and reliability issues present a major challenge for future SRAM trends. Non-intrusive and accurate SRAM stability measurement is crucial for estimating yield in large SRAM arrays. Conventional SRAM variability metrics require including test structures that cannot be used to investigate cell bit fails in functional SRAM arrays. This work proposes the Word Line Voltage Margin (WLVM), defined as the maximum allowed word-line voltage drop during write operations, as a metric for the experimental characterization of write stability of SRAM cells. Their experimental measurement can be attained with minimal design modifications, while achieving good correlation with existing writability metrics. To demonstrate its feasibility, the distribution of WLVM values has been measured in an SRAM prototype implemented in 65nm CMOS technology. The dependence of the metric with the width of the transistors has been also analysed, demonstrating their utility in post-process write stability characterization.

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, the lower the reliability. Large SRAM structures, like the last-level cache (LLC), are extremely vulnerable to process variation because they are aggressively sized to satisfy high density requirements. In this paper, we propose Concertina, an LLC designed to enable reliable operation at low voltages with conventional SRAM cells. Based on the observation that for many applications the LLC contains large amounts of null data, Concertina compresses cache blocks in order that they can be allocated to cache entries with faulty cells, enabling use of 100 percent of the LLC capacity. To distribute blocks among cache entries, Concertina implements a compression- and fault-aware insertion/replacement policy that reduces the LLC miss rate. Concertina reaches the performance of an ideal system implementing an LLC that does not suffer from parameter variation with a modest storage overhead. Specifically, performance degrades by less than 2 percent, even when using small SRAM cells, which implies over 90 percent of cache entries having defective cells, and this represents a notable improvement on previously proposed techniques.

MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache

Large SRAMs are the practical bottleneck to achieve a low supply voltage, because they suffer from process variation-induced bit errors at a low supply voltage. In this paper, we present an error-resilient cache architecture that resolves the drawback of previous approaches, i.e., the performance degradation at a low supply voltage which is caused by cache misses in accesses to faulty resources. We utilize cache access locality and error-free resources in a cost-effective manner. First, we classify cache lines into fully and partially accessed groups and apply appropriate methods to each group. For the partially accessed group, we propose a method of matching memory access behavior and error locations with intra-cache line word-level remapping. In order to reduce the area overhead used to store the cache access information history, we present an access pattern-learning line-fill buffer (LFB). For the fully accessed group, we propose the utilization of error-free assist functions in the cache, i.e., a LFB and victim cache with no process variation-induced error at the target minimum supply voltage. We also present an error-aware prefetch method that allows us to utilize the error-free victim cache to achieve a further reduction in cache misses due to faulty resources. Experimental results show that the proposed method gives an average 32.6% reduction in cycles per instruction at an error rate of 0.2% with a small area overhead of 8.2%.

Design and Implementation of PAL to LVDS Video Adapter Based on FPGA

In this paper, based on the FPGA and with a PAL decoder chip, LVDS coding chip and large capacity SRAM, the design and implementation of a PAL system for analog signals to the LVDS conversion of the video signal interface board. First of all, convert the analog signal of PAL to RGB565 digital video signal, and transform the interlaced scan into progressive scan. Then, through the frame rate conversion, resolution expansion etc. algorithm method to handle. Finally, to achieve the interlaced scanning, a resolution of 720×576, 25Hz PAL analog video signal, is converted to a progressive scan, a resolution of 1024×768, 60Hz LVDS video signal transmission. After the measurement, the resolution and frame rate of the video signal conversion interface board are all meet the design requirements. It has been verified the effectiveness of scheme.

Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area

The increasing power consumption of processors has made power reduction a first-order priority in processor design. Voltage scaling is one of the most powerful power-reduction techniques introduced to date, but is limited to some minimum voltage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDMIN</sub> . Below <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDMIN</sub> on-chip SRAM cells cannot all operate reliably due to increased process variability with technology scaling. The use of larger SRAM cells, which are less sensitive to process variability, allows a reduction in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDMIN</sub> . However, since the large-scale memory structures such as last-level caches (LLCs) often determine the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDMIN</sub> of processors, these structures cannot afford to use large SRAM cells due to the resulting increase in die area. In this paper we first propose a joint optimization of LLC cell size, the number of redundant cells, and the strength of error-correction coding (ECC) to minimize total SRAM area while meeting yield and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDMIN</sub> targets. The joint use of redundant cells and ECC enables the use of smaller cell sizes while maintaining design targets. Smaller cell sizes more than make up for the extra cells required by redundancy and ECC. In 32-nm technology our joint approach yields a 27% reduction in total SRAM area (including the extra cells) when targeting 90% yield and 600 mV <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDMIN</sub> . Second, we demonstrate that the ECC used to repair defective cells can be combined with a simple architectural technique, which can also fix particle-induced soft errors, without increasing ECC strength or processor runtime.

Evaluation of direct patternable inorganic spin-on hard mask materials using electron beam lithography

Two inorganic non-chemically amplified resists (XE15CB and XE15IB) were investigated. The resists are based on hafnium oxide sulfate and spin-cast from aqueous solution. They differ in sensitivity and resolution. In contrast to other studies, the materials were coated for the first time on 300 mm wafers and exposed on a 50 kV VISTEC SB3050DW variable shaped electron beam direct writer in a near-production environment at Fraunhofer CNT. In this paper, the evaluation of this resist family and its feasibility for production will be discussed. The resists were evaluated in terms of contrast, sensitivity and resolution. The process characteristics required for CMOS manufacturing such as delay stability were also examined. Furthermore, by exposing a large SRAM pattern (design CD of 22 nm), the exposure of a real application pattern was demonstrated.

Distributed Packet Buffers for High-Bandwidth Switches and Routers

High-speed routers rely on well-designed packet buffers that support multiple queues, provide large capacity and short response times. Some researchers suggested combined SRAM/DRAM hierarchical buffer architectures to meet these challenges. However, these architectures suffer from either large SRAM requirement or high time-complexity in the memory management. In this paper, we present scalable, efficient, and novel distributed packet buffer architecture. Two fundamental issues need to be addressed to make this architecture feasible: 1) how to minimize the overhead of an individual packet buffer; and 2) how to design scalable packet buffers using independent buffer subsystems. We address these issues by first designing an efficient compact buffer that reduces the SRAM size requirement by (k-1)/k. Then, we introduce a feasible way of coordinating multiple subsystems with a load-balancing algorithm that maximizes the overall system performance. Both theoretical analysis and experimental results demonstrate that our load-balancing algorithm and the distributed packet buffer architecture can easily scale to meet the buffering needs of high bandwidth links and satisfy the requirements of scale and support for multiple queues.

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

Hybrid main memories composed of DRAM as a cache to scalable non-volatile memories such as phase-change memory (PCM) can provide much larger storage capacity than traditional main memories. A key challenge for enabling high-performance and scalable hybrid memories, though, is efficiently managing the metadata (e.g., tags) for data cached in DRAM at a fine granularity. Based on the observation that storing metadata off-chip in the same row as their data exploits DRAM row buffer locality, this paper reduces the overhead of fine-granularity DRAM caches by only caching the metadata for recently accessed rows on-chip using a small buffer. Leveraging the flexibility and efficiency of such a fine-granularity DRAM cache, we also develop an adaptive policy to choose the best granularity when migrating data into DRAM. On a hybrid memory with a 512MB DRAM cache, our proposal using an 8KB on-chip buffer can achieve within 6% of the performance of, and 18% better energy efficiency than, a conventional 8MB SRAM metadata store, even when the energy overhead due to large SRAM metadata storage is not considered.

Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations

SRAM cell minimum operation voltage (Vmin) exhibits a skewed distribution in the presence of random parametric variations. Standard Monte Carlo (MC) simulation is prohibitively expensive to estimate the tail of the Vmin distribution for large SRAMs. We propose a fast and accurate method to estimate Vmin based on the statistical trend of static noise margin with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> scaling. Our preliminary work has shown its efficiency for standby Vmin estimation. In this work, we extend the method to estimate read and write Vmin and yield. We also generalize it for both symmetric and asymmetric types of cells. With comparable accuracy, the proposed model offers a huge speedup over standard MC. Compared with an alternative fast MC method, importance sampling, it shows a good agreement with less complexity.

Impact of circuit assist methods on margin and performance in 6T SRAM

Large scale 6T SRAM beyond 65 nm will increasingly rely on assist methods to overcome the functional limitations associated with scaling and the inherent read stability/write margin trade off. The primary focus of the circuit assist methods has been improved read or write margin with less attention given to the implications for performance. In this work, we introduce margin sensitivity and margin/delay analysis tools for assessing the functional effectiveness of the bias based assist methods and show the direct implications on voltage sensitive yield. A margin/delay analysis of bias based circuit assist methods is presented, highlighting the assist impact on the functional metrics, margin and performance. A means of categorizing the assist methods is developed to provide a first order understanding of the underlying mechanisms. The analysis spans four generations of low power technologies to show the trends and long term effectiveness of the circuit assist techniques in future low power bulk technologies.

Branch target buffer design for embedded processors

The demand for embedded application processors that support multi-tasking operating system and can execute complex applications bring them closer to general purpose processors. These strong processors have a limited power source because they are usually found in portable devices such as smartphones and other PDAs, and are powered by batteries. The Branch Target Buffer (BTB), which is commonly used in general purpose processors, is becoming prevalent in high-end embedded processors in order to support long pipelines and mitigate high miss penalties. However, the BTB is a major power consumer because it is a large SRAM structure that is accessed almost every cycle. We propose two BTB designs that fit the tight power budgets of embedded processors. In the first design, the power consumption of a single BTB access is reduced by reading only the lower part of the predicted target address bits. This design has power savings of up to 25% dynamic power, with effectively no performance degradation. In the second design, we avoid redundant BTB accesses to the same set by using a small buffer that holds the most recently accessed set. This design results in 75% dynamic power savings at the cost of up to 0.64% system slowdown in a 2-way BTB, and 80% dynamic power savings at the cost of up to 0.58% system slowdown in a 4-way BTB.