Large-scale Quantum Computers Research Articles

Learning high-accuracy error decoding for quantum processors

Building a large-scale quantum computer requires effective strategies to correct errors that inevitably arise in physical quantum systems1. Quantum error-correction codes2 present a way to reach this goal by encoding logical information redundantly into many physical qubits. A key challenge in implementing such codes is accurately decoding noisy syndrome information extracted from redundancy checks to obtain the correct encoded logical information. Here we develop a recurrent, transformer-based neural network that learns to decode the surface code, the leading quantum error-correction code3. Our decoder outperforms other state-of-the-art decoders on real-world data from Google’s Sycamore quantum processor for distance-3 and distance-5 surface codes4. On distances up to 11, the decoder maintains its advantage on simulated data with realistic noise including cross-talk and leakage, utilizing soft readouts and leakage information. After training on approximate synthetic data, the decoder adapts to the more complex, but unknown, underlying error distribution by training on a limited budget of experimental samples. Our work illustrates the ability of machine learning to go beyond human-designed algorithms by learning from data directly, highlighting machine learning as a strong contender for decoding in quantum computers.

Modular Quantum Processor with an All-to-All Reconfigurable Router

Superconducting qubits provide a promising approach to large-scale fault-tolerant quantum computing. However, qubit connectivity on a planar surface is typically restricted to only a few neighboring qubits. Achieving longer-range and more flexible connectivity, which is particularly appealing in light of recent developments in error-correcting codes, however, usually involves complex multilayer packaging and external cabling, which is resource intensive and can impose fidelity limitations. Here, we propose and realize a high-speed on-chip quantum processor that supports reconfigurable all-to-all coupling with a large on-off ratio. We implement the design in a four-node quantum processor, built with a modular design comprising a wiring substrate coupled to two separate qubit-bearing substrates, each including two single-qubit nodes. We use this device to demonstrate reconfigurable controlled-Z gates across all qubit pairs, with a benchmarked average fidelity of 96.00%±0.08% and best fidelity of 97.14%±0.07%, limited mainly by dephasing in the qubits. We also generate multiqubit entanglement, distributed across the separate modules, demonstrating GHZ-3 and GHZ-4 states with fidelities of 88.15%±0.24% and 75.18%±0.11%, respectively. This approach promises efficient scaling to larger-scale quantum circuits and offers a pathway for implementing quantum algorithms and error-correction schemes that benefit from enhanced qubit connectivity. Published by the American Physical Society 2024

Electrodynamics-based quantum gate optimization with born scattering

In this paper, we propose employing electron scattering to realize unitary quantum gates that are controlled by three qubits. Using Feynman’s rules, we find an expression for the transition amplitude for scattering from an external electromagnetic source. In this context, the scattering amplitude is modeled as a unitary gate whose state can be regulated. The optimal value of the vector potential needed to implement the gate is obtained by minimizing the difference between the designed gate and the target gate, with the total energy consumed as a constraint. The design algorithm is obtained by discretizing the resulting integral equations into vector equations. This design algorithm can be applied in various fields such as quantum computing, communication, and sensing. It offers a promising approach for developing efficient and accurate gates for quantum information processing. Furthermore, this approach can also be extended to design gates for multi-qubit systems, which are essential for large-scale quantum computing. The use of this algorithm can significantly contribute to the development of practical quantum technologies.

Scalable on-chip multiplexing of silicon single and double quantum dots

Owing to the maturity of complementary metal oxide semiconductor (CMOS) microelectronics, qubits realized with spins in silicon quantum dots (QDs) are considered among the most promising technologies for building scalable quantum computers. For this goal, ultra-low-power on-chip cryogenic CMOS (cryo-CMOS) electronics for control, read-out, and interfacing of the qubits is an important milestone. We report on-chip interfacing of tunable electron and hole QDs by a 64-channel cryo-CMOS multiplexer with less-than-detectable static power dissipation. We analyze charge noise and measure state-of-the-art addition energies and gate lever arm parameters in the QDs. We correlate low noise in QDs and sharp turn-on characteristics in cryogenic transistors, both fabricated with the same gate stack. Finally, we demonstrate that our hybrid quantum-CMOS technology provides a route to scalable interfacing of a large number of QD devices, enabling, for example, variability analysis and QD qubit geometry optimization, which are prerequisites for building large-scale silicon-based quantum computers.

A short-list of pairing-friendly curves resistant to the Special TNFS algorithm at the 192-bit security level

For more than two decades, pairings have been a fundamental tool for designing elegant cryptosystems, varying from digital signature schemes to more complex privacy-preserving constructions. However, the advancement of quantum computing threatens to undermine public-key cryptography. Concretely, it is widely accepted that a future large-scale quantum computer would be capable to break any public-key cryptosystem used today, rendering today's public-key cryptography obsolete and mandating the transition to quantum-safe cryptographic solutions. This necessity is enforced by numerous recognized government bodies around the world, including NIST which initiated the first open competition in standardizing post-quantum (PQ) cryptographic schemes, focusing primarily on digital signatures and key encapsulation/public-key encryption schemes. Despite the current efforts in standardizing PQ primitives, the landscape of complex, privacy-preserving cryptographic protocols, e.g., zkSNARKs/zkSTARKs, is at an early stage. Existing solutions suffer from various disadvantages in terms of efficiency and compactness and in addition, they need to undergo the required scrutiny to gain the necessary trust in the academic and industrial domains. Therefore, it is believed that the migration to purely quantum-safe cryptography would require an intermediate step where current classically secure protocols and quantum-safe solutions will co-exist. This is enforced by the report of the Commercial National Security Algorithm Suite version 2.0, mandating transition to quantum-safe cryptographic algorithms by 2033 and suggesting to incorporate ECC at 192-bit security in the meantime. To this end, the present paper aims at providing a comprehensive study on pairings at 192-bit security level. We start with an exhaustive review in the literature to search for all possible recommendations of such pairing constructions, from which we extract the most promising candidates in terms of efficiency and security, with respect to the advanced Special TNFS attacks. Our analysis is focused, not only on the pairing computation itself, but on additional operations that are relevant in pairing-based applications, such as hashing to pairing groups, cofactor clearing and subgroup membership testing. We implement all functionalities of the most promising candidates within the RELIC cryptographic toolkit in order to identify the most efficient pairing implementation at 192-bit security and provide extensive experimental results.

Leveraging HLS to Design a Versatile & High-Performance Classic McEliece Accelerator

By harnessing fundamental quantum properties, a large-scale quantum computer could undermine currently deployed public-key algorithms. The post-quantum, code-based cryptosystem Classic McEliece (CM) addresses this security concern. However, its large public key size (up to 1.3MB) poses various hardware implementation challenges. In this paper, we focus on the high memory bandwidth requirements of the CM encoding function, in the context of heterogeneous CPU-FPGA devices. More concretely, we target the acceleration of public-key loading and processing from any globally-shared or accelerator-private memory system. We present a novel and constant-time accelerator eEnc that exploits the elevated parallelization potential of FPGA devices to yield high-performance results. Our accelerator implements the encoding and the random error vector generation functions, which comprise the main computational load of Encapsulation. Two accelerator design variants are introduced, providing different hardware tradeoffs. Regarding intra-accelerator data communication, and unlike other state-of-the-art (SOTA) works, we combine a streaming protocol with task-level parallelization to remove the need to store the public key in accelerator-private memories. Our proposed design shows new record execution times over its SOTA counterparts, ranging on average from 3.5 × up to 7.7 × across the five security level parameter sets. Our end-to-end implementation in a Zynq SoC shows an average speedup of 2.2 × compared to a 64-bit vectorized CM software-baseline. The elevated logic resource consumption, characteristic of HLS designs, can be readily adjusted with a performance tradeoff.

Low Disorder and High Mobility 2DEG in Si/SiGe Fabricated in 200 mm BiCMOS Pilot line

Spin qubits based on quantum dots built on Si/SiGe heterostructures are a leading contender for achieving large-scale quantum computation. The quality of quantum dots fabricated on these heterostructures is directly connected to the quality of the 2D electron gas (2DEG) confined in the strained Silicon quantum well. The properties of such 2DEG can be readily assessed using Hall bar-shaped field-effect transistors (HB-FETs) and magneto-transport measurements, enabling a faster feedback loop for heterostructure optimization process. In this work, we present our recent progress in enabling silicon-based quantum computation by demonstrating fundamental components for 2DEG characterization, all developed in IHP's 200 mm BiCMOS pilot line. We demonstrate fully functional HB-FETs on Si/SiGe heterostructures grown on 200 mm silicon wafers, showcasing state-of-the-art 2DEG with maximum carrier mobility exceeding 300,000 cm²/Vs and a percolation threshold of 6.3×1010 cm⁻². These results will help advance spin qubit research based on Si/SiGe heterostructures.

High-fidelity teleportation of a logical qubit using transversal gates and lattice surgery

Quantum state teleportation is commonly used in designs for large-scale quantum computers. Using Quantinuum’s H2 trapped-ion quantum processor, we demonstrate fault-tolerant state teleportation circuits for a quantum error correction code—specifically the Steane code. The circuits use up to 30 qubits at the physical level and employ real-time quantum error correction. We conducted experiments on several variations of logical teleportation circuits using both transversal gates and lattice surgery. We measured the logical process fidelity to be 0.975 ± 0.002 for the transversal teleportation implementation and 0.851 ± 0.009 for the lattice surgery teleportation implementation as well as 0.989 ± 0.002 for an implementation of Knill-style quantum error correction.

Electromagnetically Induced Transparency Cooling of High-Nuclear-Spin Ions.

We report the electromagnetically induced transparency (EIT) cooling of ^{137}Ba^{+} ions with a nuclear spin of I=3/2, which are a good candidate of qubits for future large-scale trapped-ion quantum computing. EIT cooling of atoms or ions with a complex ground-state level structure is challenging due to the lack of an isolated Λ system, as the population can escape from the Λ system to reduce the cooling efficiency. We overcome this issue by leveraging an EIT pumping laser to repopulate the cooling subspace, ensuring continuous and effective EIT cooling. We cool the two radial modes of a single ^{137}Ba^{+} ion to average motional occupations of 0.08(5) and 0.15(7), respectively. Using the same laser parameters, we also cool all the ten radial modes of a five-ion chain to near their ground states. Our approach can be adapted to atomic species possessing similar level structures. It allows engineering of the EIT Fano-like spectrum, which can be useful for simultaneous cooling of modes across a wide frequency range, aiding in large-scale trapped-ion quantum information processing.

Entangling gates on degenerate spin qubits dressed by a global field

Semiconductor spin qubits represent a promising platform for future large-scale quantum computers owing to their excellent qubit performance, as well as the ability to leverage the mature semiconductor manufacturing industry for scaling up. Individual qubit control, however, commonly relies on spectral selectivity, where individual microwave signals of distinct frequencies are used to address each qubit. As quantum processors scale up, this approach will suffer from frequency crowding, control signal interference and unfeasible bandwidth requirements. Here, we propose a strategy based on arrays of degenerate spins coherently dressed by a global control field and individually addressed by local electrodes. We demonstrate simultaneous on-resonance driving of two degenerate qubits using a global field while retaining addressability for qubits with equal Larmor frequencies. Furthermore, we implement SWAP oscillations during on-resonance driving, constituting the demonstration of driven two-qubit gates. Significantly, our findings highlight how dressing can overcome the fragility of entangling gates between superposition states and increase their noise robustness. These results constitute a paradigm shift in qubit control in order to overcome frequency crowding in large-scale quantum computing.

Delayed-measurement one-way quantum computing on cloud quantum computer

Abstract One-way quantum computation focuses on initially generating an entangled cluster state followed by a sequence of measurements with classical communication of their individual outcomes. Recently, a delayed-measurement approach has been applied to replace classical communication of individual measurement outcomes. In this work, by considering the delayed-measurement approach, we demonstrate a modified one-way CNOT gate using the on-cloud superconducting quantum computing platform: Quafu. The modified protocol for one-way quantum computing requires only three qubits rather than the four used in the standard protocol. Since this modified cluster state decreases the number of physical qubits required to implement one-way computation, both the scalability and complexity of the computing process are improved. Compared to previous work, this modified one-way CNOT gate is superior to the standard one in both fidelity and resource requirements. We have also numerically compared the behavior of standard and modified methods in large-scale one-way quantum computing. Our results suggest that in a noisy intermediate-scale quantum (NISQ) era, the modified method shows a significant advantage for one-way quantum computation.

Bolometric detection of Josephson radiation

One of the most promising approaches towards large-scale quantum computation uses devices based on many Josephson junctions. Yet, even today, open questions regarding the single junction remain unsolved, such as the detailed understanding of the quantum phase transitions, the coupling of the Josephson junction to the environment or how to improve the coherence of a superconducting qubit. Here we design and build an engineered on-chip reservoir connected to a Josephson junction that acts as an efficient bolometer for detecting the Josephson radiation under non-equilibrium, that is, biased conditions. The bolometer converts the a.c. Josephson current at microwave frequencies up to about 100 GHz into a temperature rise measured by d.c. thermometry. A circuit model based on realistic parameter values captures both the current–voltage characteristics and the measured power quantitatively. The present experiment demonstrates an efficient, wide-band, thermal detection scheme of microwave photons and provides a sensitive detector of Josephson dynamics beyond the standard conductance measurements.

Coupling and characterization of a Si/SiGe triple quantum dot array with a microwave resonator

Abstract Scaling up spin qubits in silicon-based quantum dots is one of the pivotal challenges in achieving large-scale semiconductor quantum computation. To satisfy the connectivity requirements and reduce the lithographic complexity, utilizing the qubit array structure and the circuit quantum electrodynamics (cQED) architecture together is expected to be a feasible scaling scheme. A triple-quantum dot (TQD) coupled with a superconducting resonator is regarded as a basic cell to demonstrate this extension scheme. In this article, we investigate a system consisting of a silicon TQD and a high-impedance TiN coplanar waveguide (CPW) resonator. The TQD can couple to the resonator via the right double-quantum dot (RDQD), which reaches the strong coupling regime with a charge–photon coupling strength of g 0/(2π) = 175 MHz. Moreover, we illustrate the high tunability of the TQD through the characterization of stability diagrams, quadruple points (QPs), and the quantum cellular automata (QCA) process. Our results contribute to fostering the exploration of silicon-based qubit integration.

Optimizing Dilithium Implementation with AVX2/-512

Dilithium is a signature scheme that is currently being standardized to the Module-Lattice-Based Digital Signature Standard by NIST. It is believed to be secure even against attacks from large-scale quantum computers based on lattice problems. The implementation efficiency is important for promoting the migration of current cryptography algorithms to post-quantum cryptography algorithms. In this paper, we optimize the implementation of Dilithium with several new approaches proposed. Firstly, we improve the efficiency of parallel NTT implementations. The overhead of shuffling operations is reduced in our implementations, and fewer loading instructions are invoked for the precomputations. Then, we optimize the sampling and bit-packing of polynomial coefficients in Dilithium. We can handle double the number of coefficients within one register using a new approach for the sampling of secret key polynomials. The approaches proposed in this paper are applicable to implementations under AVX2 and AVX-512 instruction sets. Take Dilithium2 as an illustration, our AVX2 implementation demonstrates improvements of 22.7%, 16.9%, and 13.5% for KeyGen, Sign, and Verify compared to the previous implementation.

Demonstration of Fault-Tolerant Steane Quantum Error Correction

Encoding information redundantly using quantum error-correcting (QEC) codes allows one to overcome the inherent sensitivity to noise in quantum computers to ultimately achieve large-scale quantum computation. The Steane QEC method involves preparing an auxiliary logical qubit of the same QEC code as used for the data register. The data and auxiliary registers are then coupled with a logical controlled- () gate, enabling a measurement of the auxiliary register to reveal the error syndrome. This study presents the implementation of multiple rounds of fault-tolerant (FT) Steane QEC on a trapped-ion quantum computer. Various QEC codes are employed and the results are compared to a previous experimental approach utilizing flag qubits. Our experimental findings show improved logical fidelities for Steane QEC and accompanying numerical simulations indicate an even larger performance advantage for quantum processors limited by entangling-gate errors. This establishes experimental Steane QEC as a competitive paradigm for FT quantum computing. Published by the American Physical Society 2024

Programmable silicon-photonic quantum simulator based on a linear combination of unitaries

Simulating the dynamic evolution of physical and molecular systems in a quantum computer is of fundamental interest in many applications. The implementation of dynamics simulation requires efficient quantum algorithms. The Lie-Trotter-Suzuki approximation algorithm, also known as the Trotterization, is basic in Hamiltonian dynamics simulation. A multi-product algorithm that is a linear combination of multiple Trotterizations has been proposed to improve the approximation accuracy. However, implementing such multi-product Trotterization in quantum computers remains challenging due to the requirements of highly controllable and precise quantum entangling operations with high success probability. Here, we report a programmable integrated-photonic quantum simulator based on a linear combination of unitaries, which can be tailored for implementing the linearly combined multiple Trotterizations, and on the simulator we benchmark quantum simulation of Hamiltonian dynamics. We modify the multi-product algorithm by integrating it with oblivious amplitude amplification to simultaneously reach high simulation precision and high success probability. The quantum simulator is devised and fabricated on a large-scale silicon-photonic quantum chip, which allows the initialization, manipulation, and measurement of arbitrary four-qubit states and linearly combined unitary gates. As an example, the quantum simulator is reprogrammed to emulate the dynamics of an electron spin and nuclear spin coupled system. This work promises the practical dynamics simulations of real-world physical and molecular systems in future large-scale quantum computers.

Valley-Free Silicon Fins Caused by Shear Strain.

Electron spins confined in silicon quantum dots are promising candidates for large-scale quantum computers. However, the degeneracy of the conduction band of bulk silicon introduces additional levels dangerously close to the window of computational energies, where the quantum information can leak. The energy of the valley states-typically 0.1meV-depends on hardly controllable atomistic disorder and still constitutes a fundamental limit to the scalability of these architectures. In this work, we introduce designs of complementary metal-oxide-semiconductor (CMOS)-compatible silicon fin field-effect transistors that enhance the energy gap to noncomputational states by more than one order of magnitude. Our devices comprise realistic silicon-germanium nanostructures with a large shear strain, where troublesome valley degrees of freedom are completely removed. The energy of noncomputational states is therefore not affected by unavoidable atomistic disorder and can further be tuned insitu by applied electric fields. Our design ideas are directly applicable to a variety of setups and will offer a blueprint toward silicon-based large-scale quantum processors.

A cryogenic on-chip microwave pulse generator for large-scale superconducting quantum computing

For superconducting quantum processors, microwave signals are delivered to each qubit from room-temperature electronics to the cryogenic environment through coaxial cables. Limited by the heat load of cabling and the massive cost of electronics, such an architecture is not viable for millions of qubits required for fault-tolerant quantum computing. Monolithic integration of the control electronics and the qubits provides a promising solution, which, however, requires a coherent cryogenic microwave pulse generator that is compatible with superconducting quantum circuits. Here, we report such a signal source driven by digital-like signals, generating pulsed microwave emission with well-controlled phase, intensity, and frequency directly at millikelvin temperatures. We showcase high-fidelity readout of superconducting qubits with the microwave pulse generator. The device demonstrated here has a small footprint, negligible heat load, great flexibility to operate, and is fully compatible with today’s superconducting quantum circuits, thus providing an enabling technology for large-scale superconducting quantum computers.

Theoretical proposal for a broadband on-chip multistage quantum amplifier

A broadband on-chip multistage quantum amplifier (MQA) for reading out multiple superconducting qubits is proposed. The bandwidth of quantum amplifier is enhanced by concatenating amplifiers with modular nonreciprocal elements, which are superconducting isolators and circulators based on tunable inductor bridge. The circuit model of MQA is built and simulated. The variation of bandwidth, gain and gain-bandwidth product (GBP) of MQA with the number of stages and bandpass of the constitutive amplifiers are simulated. It is revealed that the bandwidth can be as large as ∼3.2 GHz with a gain of 20 dB at 4–8 GHz frequency range. For a 4-stage MQA composed of four quantum amplifiers with 20 dB gain and 0.3 GHz BW-pass, the bandwidth is 2.14 GHz at 20 dB gain, which is quite cost-efficient. Due to its non-reciprocity, MQA can effectively prevent signals from reflecting to quantum processors. In addition, MQA breaks the limitation of GBP and is easy to integrate with superconducting circuits. The MQA would play a crucial role in the high-fidelity readout of multiple qubits in large-scale superconducting quantum computers.

Application of RFSoC-based arbitrary waveform generator for coherent control of atomic qubits

This study evaluates an AMD Zynq Ultrascale+ RF System-on-Chip (RFSoC) as an arbitrary waveform generator (AWG) for controlling atomic qubits coherently. We explore the advantages of using an RFSoC-based AWG for atomic qubit manipulation and experimentally demonstrate its utility in quantum computing. Our findings demonstrate that RFSoC is a scalable solution for developing large-scale quantum computers with atomic qubits, offering a promising approach for applications.