Large-scale Quantum Computers Research Articles

Programmable silicon-photonic quantum simulator based on a linear combination of unitaries

Simulating the dynamic evolution of physical and molecular systems in a quantum computer is of fundamental interest in many applications. The implementation of dynamics simulation requires efficient quantum algorithms. The Lie-Trotter-Suzuki approximation algorithm, also known as the Trotterization, is basic in Hamiltonian dynamics simulation. A multi-product algorithm that is a linear combination of multiple Trotterizations has been proposed to improve the approximation accuracy. However, implementing such multi-product Trotterization in quantum computers remains challenging due to the requirements of highly controllable and precise quantum entangling operations with high success probability. Here, we report a programmable integrated-photonic quantum simulator based on a linear combination of unitaries, which can be tailored for implementing the linearly combined multiple Trotterizations, and on the simulator we benchmark quantum simulation of Hamiltonian dynamics. We modify the multi-product algorithm by integrating it with oblivious amplitude amplification to simultaneously reach high simulation precision and high success probability. The quantum simulator is devised and fabricated on a large-scale silicon-photonic quantum chip, which allows the initialization, manipulation, and measurement of arbitrary four-qubit states and linearly combined unitary gates. As an example, the quantum simulator is reprogrammed to emulate the dynamics of an electron spin and nuclear spin coupled system. This work promises the practical dynamics simulations of real-world physical and molecular systems in future large-scale quantum computers.

Valley-Free Silicon Fins Caused by Shear Strain.

Electron spins confined in silicon quantum dots are promising candidates for large-scale quantum computers. However, the degeneracy of the conduction band of bulk silicon introduces additional levels dangerously close to the window of computational energies, where the quantum information can leak. The energy of the valley states-typically 0.1meV-depends on hardly controllable atomistic disorder and still constitutes a fundamental limit to the scalability of these architectures. In this work, we introduce designs of complementary metal-oxide-semiconductor (CMOS)-compatible silicon fin field-effect transistors that enhance the energy gap to noncomputational states by more than one order of magnitude. Our devices comprise realistic silicon-germanium nanostructures with a large shear strain, where troublesome valley degrees of freedom are completely removed. The energy of noncomputational states is therefore not affected by unavoidable atomistic disorder and can further be tuned insitu by applied electric fields. Our design ideas are directly applicable to a variety of setups and will offer a blueprint toward silicon-based large-scale quantum processors.

A cryogenic on-chip microwave pulse generator for large-scale superconducting quantum computing

For superconducting quantum processors, microwave signals are delivered to each qubit from room-temperature electronics to the cryogenic environment through coaxial cables. Limited by the heat load of cabling and the massive cost of electronics, such an architecture is not viable for millions of qubits required for fault-tolerant quantum computing. Monolithic integration of the control electronics and the qubits provides a promising solution, which, however, requires a coherent cryogenic microwave pulse generator that is compatible with superconducting quantum circuits. Here, we report such a signal source driven by digital-like signals, generating pulsed microwave emission with well-controlled phase, intensity, and frequency directly at millikelvin temperatures. We showcase high-fidelity readout of superconducting qubits with the microwave pulse generator. The device demonstrated here has a small footprint, negligible heat load, great flexibility to operate, and is fully compatible with today’s superconducting quantum circuits, thus providing an enabling technology for large-scale superconducting quantum computers.

A site-resolved two-dimensional quantum simulator with hundreds of trapped ions.

A large qubit capacity and an individual readout capability are two crucial requirements for large-scale quantum computing and simulation1. As one of the leading physical platforms for quantum information processing, the ion trap has achieved a quantum simulation of tens of ions with site-resolved readout in a one-dimensional Paul trap2-4 and of hundreds of ions with global observables in a two-dimensional (2D) Penning trap5,6. However, integrating these two features into a single system is still very challenging. Here we report the stable trapping of 512 ions in a 2D Wigner crystal and the sideband cooling of their transverse motion. We demonstrate the quantum simulation of long-range quantum Ising models with tunable coupling strengths and patterns, with or without frustration, using 300 ions. Enabled by the site resolution in the single-shot measurement, we observe rich spatial correlation patterns in the quasi-adiabatically prepared ground states, which allows us to verify quantum simulation results by comparingthe measured two-spin correlations with the calculated collective phonon modes and with classical simulated annealing. We further probe the quench dynamics of the Ising model in a transverse field to demonstrate quantum sampling tasks. Our work paves the way for simulating classically intractable quantum dynamics and for running noisy intermediate-scale quantum algorithms7,8 using 2D ion trap quantum simulators.

Anisotropic exchange interaction of two hole-spin qubits

Semiconductor spin qubits offer the potential to employ industrial transistor technology to produce large-scale quantum computers. Silicon hole spin qubits benefit from fast all-electrical qubit control and sweet spots to counteract charge and nuclear spin noise. However, the demonstration of a two-qubit interaction has remained an open challenge. One missing factor is an understanding of the exchange coupling in the presence of a strong spin–orbit interaction. Here we study two hole-spin qubits in a silicon fin field-effect transistor, the workhorse device of today’s semiconductor industry. We demonstrate electrical tunability of the exchange splitting from above 500 MHz to close-to-off and perform a conditional spin-flip in 24 ns. The exchange is anisotropic because of the spin–orbit interaction. Upon tunnelling from one quantum dot to the other, the spin is rotated by almost 180 degrees. The exchange Hamiltonian no longer has the Heisenberg form and can be engineered such that it enables two-qubit controlled rotation gates without a trade-off between speed and fidelity. This ideal behaviour applies over a wide range of magnetic field orientations, rendering the concept robust with respect to variations from qubit to qubit, indicating that it is a suitable approach for realizing a large-scale quantum computer.

Simulations of superconducting quantum gates by digital flux tuner for qubits

Abstract The interconnection bottleneck caused by limitations of cable number, inner space and cooling power of dilution refrigerators has been an outstanding challenge for building scalable superconducting quantum computers with the increasing number of qubits in quantum processors. To surmount such an obstacle, it is desirable to integrate qubits with quantum–classical interface (QCI) circuits based on rapid single flux quantum (RSFQ) circuits. In this work, a digital flux tuner for qubits (DFTQ) is proposed for manipulating flux of qubits as a crucial part of the interface circuit. A schematic diagram of the DFTQ is presented, consisting of a coarse tuning unit and a fine-tuning unit for providing magnetic flux with different precision to qubits. The method of using DFTQ to provide flux for gate operations is discussed from the optimization of circuit design and input signal. To verify the effectiveness of the method, simulations of a single DFTQ and quantum gates including a Z gate and an iSWAP gate with DFTQs are performed for flux-tunable transmons. The quantum process tomography corresponding to the two gates is also carried out to analyze the sources of gate error. The results of tomography show that the gate fidelities independent of the initial states of the Z gate and the iSWAP gate are 99.935% and 99.676%, respectively. With DFTQs inside, the QCI would be a powerful tool for building large-scale quantum computers.

Theoretical proposal for a broadband on-chip multistage quantum amplifier

Abstract A broadband on-chip multistage quantum amplifier (MQA) for reading out multiple superconducting qubits is proposed. The bandwidth of quantum amplifier is enhanced by concatenating amplifiers with modular nonreciprocal elements, which are superconducting isolators and circulators based on tunable inductor bridge. The circuit model of MQA is built and simulated. The variation of bandwidth, gain and Gain-bandwidth Product (GBP) of MQA with the number of stages and bandpass of the constitutive amplifiers are simulated. It is revealed that the bandwidth can be as large as ∼ 3.2 GHz with a gain of 20 dB at 4-8 GHz frequency range. For a 4-stage MQA composed of four quantum amplifiers with 20 dB gain and 0.3 GHz BW-pass, the bandwidth is 2.14 GHz at 20 dB gain, which is quite cost-efficient. Due to its non-reciprocity, MQA can effectively prevent signals from reflecting to quantum processors. In addition, MQA breaks the limitation of GBP and is easy to integrate with superconducting circuits. The MQA would play a crucial role in the high-fidelity readout of multiple qubits in large-scale superconducting quantum computers.

Bilayer ion trap design for 2D arrays

Junctions are fundamental elements that support qubit locomotion in two-dimensional ion trap arrays and enhance connectivity in emerging trapped-ion quantum computers. In surface ion traps they have typically been implemented by shaping radio frequency (RF) electrodes in a single plane to minimize the disturbance to the pseudopotential. However, this method introduces issues related to RF lead routing that can increase power dissipation and the likelihood of voltage breakdown. Here, we propose and simulate a novel two-layer junction design incorporating two perpendicularly rotoreflected (rotated, then reflected) linear ion traps. The traps are vertically separated, and create a trapping potential between their respective planes. The orthogonal orientation of the RF electrodes of each trap relative to the other provides perpendicular axes of confinement that can be used to realize transport in two dimensions. While this design introduces manufacturing and operating challenges, as now two separate structures have to be precisely positioned relative to each other in the vertical direction and optical access from the top is obscured, it obviates the need to route RF leads below the top surface of the trap and eliminates the pseudopotential bumps that occur in typical junctions. In this paper the stability of idealized ion transfer in the new configuration is demonstrated, both by solving the Mathieu equation analytically to identify the stable regions and by numerically modeling ion dynamics. Our novel junction layout has the potential to enhance the flexibility of microfabricated ion trap control to enable large-scale trapped-ion quantum computing.

Fast joint parity measurement via collective interactions induced by stimulated emission

Parity detection is essential in quantum error correction. Error syndromes coded in parity are detected routinely by sequential CNOT gates. Here, different from the standard CNOT-gate based scheme, we propose a reliable joint parity measurement (JPM) scheme inspired by stimulated emission. By controlling the collective behavior between data qubits and syndrome qubit, we realize the parity detection and experimentally implement the weight-2 and weight-4 JPM scheme in a tunable coupling superconducting circuit, which shows comparable performance to the CNOT scheme. Moreover, with the aid of the coupling tunability in quantum system, this scheme can be further utilized for specific joint entangling state preparation (JEP) with high fidelity, such as multiqubit entangled state preparation for non-adjacent qubits. This strategy, combined with the superconducting qubit system with tunable couplers, reveals tremendous potential and applications in the surface code architecture without adding extra circuit elements. Besides, the method we develop here can readily be applied in large-scale quantum computation and quantum simulation.

Heralded Three-Photon Entanglement from a Single-Photon Source on a Photonic Chip.

In the quest to build general-purpose photonic quantum computers, fusion-based quantum computation has risen to prominence as a promising strategy. This model allows a ballistic construction of large cluster states which are universal for quantum computation, in a scalable and loss-tolerant way without feed forward, by fusing many small n-photon entangled resource states. However, a key obstacle to this architecture lies in efficiently generating the required essential resource states on photonic chips. One such critical seed state that has not yet been achieved is the heralded three-photon Greenberger-Horne-Zeilinger (3-GHZ) state. Here, we address this elementary resource gap, by reporting the first experimental realization of a heralded 3-GHZ state. Our implementation employs a low-loss and fully programmable photonic chip that manipulates six indistinguishable single photons of wavelengths in the telecommunication regime. Conditional on the heralding detection, we obtain the desired 3-GHZ state with a fidelity 0.573±0.024. Our Letter marks an important step for the future fault-tolerant photonic quantum computing, leading to the acceleration of building a large-scale optical quantum computer.

Post-Quantum Signatures on RISC-V with Hardware Acceleration

CRYSTALS-Dilithium and Falcon are digital signature algorithms based on cryptographic lattices, which are considered secure even if large-scale quantum computers will be able to break conventional public-key cryptography. Both schemes have been selected for standardization in the NIST Post-Quantum competition. In this work, we present a RISC-V HW/SW codesign that aims to combine the advantages of software and hardware implementations, i.e., flexibility and performance. It shows the use of flexible hardware accelerators, which have been previously used for Public-Key Encryption (PKE) and Key-Encapsulation Mechanism (KEM), for Post-Quantum signatures. It is optimized for Dilithium as a generic signature scheme but also accelerates applications that require fast verification of Falcon’s compact signatures. We provide a comparison with previous works showing that for Dilithium and Falcon, cycle counts are significantly reduced, such that our design is faster than previous software implementations or other HW/SW codesigns. In addition to that, we present a compact Globalfoundries 22nm ASIC design that runs at 800 MHz. By using hardware acceleration, energy consumption for Dilithium is reduced by up to 92.2%, and up to 67.5% for Falcon’s signature verification.

Agile Acceleration of Stateful Hash-based Signatures in Hardware

With the development of large-scale quantum computers, the current landscape of asymmetric cryptographic algorithms will change dramatically. Today’s standards like RSA, DSA, and ElGamal will no longer provide sufficient security against quantum attackers and need to be replaced with novel algorithms. In the face of these developments, NIST has already started a standardization process for new Key Encapsulation Mechanisms (KEMs) and Digital Signatures (DSs). Moreover, NIST has recommended the two stateful Hash-Based Signatures (HBSs) schemes XMSS and LMS for use in devices with a long expected lifetime and limited capabilities for maintenance. Both schemes are also standardized by the IETF. In this work, we present the first agile hardware implementation that supports both LMS and XMSS. Our design can instantiate either LMS, XMSS, or both schemes using a simple configuration setting. Leveraging the vast similarities of the two schemes, the hardware utilization of the agile design increases by 20% in LUTs and only 3% in Flip Flops (FFs) over a standalone XMSS implementation. Furthermore, our approach can easily be configured with an arbitrary number of hash cores and accelerators for the one-time signatures for different application scenarios. We evaluate our implementation on the Xilinx Artix-7 FPGA platform, which is the recommended target for PQC implementations by NIST. We explore potential tradeoffs in the design space and compare our results to previous work in this field.

Penning micro-trap for quantum computing.

Trapped ions in radio-frequency traps are among the leading approaches for realizing quantum computers, because of high-fidelity quantum gates and long coherence times1-3. However, the use of radio-frequencies presents several challenges to scaling, including requiring compatibility of chips with high voltages4, managing power dissipation5 and restricting transport and placement of ions6. Here we realize a micro-fabricated Penning ion trap that removes these restrictions by replacing the radio-frequency field with a 3T magnetic field. We demonstrate full quantum control of an ion in this setting, as well as the ability to transport the ion arbitrarily in the trapping plane above the chip. This unique feature of the Penning micro-trap approach opens up a modification of the quantum charge-coupled device architecture with improved connectivity and flexibility, facilitating the realization of large-scale trapped-ion quantum computing, quantum simulation and quantum sensing.

Non-symmetric Pauli spin blockade in a silicon double quantum dot

Spin qubits in gate-defined silicon quantum dots are receiving increased attention thanks to their potential for large-scale quantum computing. Readout of such spin qubits is done most accurately and scalably via Pauli spin blockade (PSB), however, various mechanisms may lift PSB and complicate readout. In this work, we present an experimental study of PSB in a multi-electron low-symmetry double quantum dot (DQD) in silicon nanowires. We report on the observation of non-symmetric PSB, manifesting as blockaded tunneling when the spin is projected to one QD of the pair but as allowed tunneling when the projection is done into the other. By analyzing the interaction of the DQD with a readout resonator, we find that PSB lifting is caused by a large coupling between the different electron spin manifolds of 7.90 μeV and that tunneling is incoherent. Further, magnetospectroscopy of the DQD in 16 charge configurations, enables reconstructing the energy spectrum of the DQD and reveals the lifting mechanism is energy-level selective. Our results indicate enhanced spin-orbit coupling which may enable all-electrical qubit control of electron spins in silicon nanowires.

Cryogenic flip-chip interconnection for silicon qubit devices

Interfacing qubits with peripheral control circuitry poses one of the major common challenges toward realization of large-scale quantum computation. Spin qubits in silicon quantum dots (QDs)are particularly promising for scaling up, owing to the potential benefits from the know-how of the semiconductor industry. In this paper, we focus on the interposer technique as one of the potential solutions for the quantum–classical interface problem and report DC and RF characterization of a silicon QD device mounted on an interposer. We demonstrate flip-chip interconnection with the qubit device down to 4.2 K by observing Coulomb diamonds. We furthermore propose and demonstrate a laser-cut technique to disconnect peripheral circuits no longer in need. These results may pave the way toward system-on-a-chip quantum–classical integration for future quantum processors.

A Survey about Post Quantum Cryptography Methods

Cryptography is an art of hiding the significant data or information with some other codes. It is a practice and study of securing information and communication. Thus, cryptography prevents third party intervention over the data communication. The cryptography technology transforms the data into some other form to enhance security and robustness against the attacks. The thrust of enhancing the security among data transfer has been emerged ever since the need of Artificial Intelligence field came into a market. Therefore, modern way of computing cryptographic algorithm came into practice such as AES, 3DES, RSA, Diffie-Hellman and ECC. These public-key encryption techniques now in use are based on challenging discrete logarithms for elliptic curves and complex factorization. However, those two difficult problems can be effectively solved with the help of sufficient large-scale quantum computer. The Post Quantum Cryptography (PQC) aims to deal with an attacker who has a large-scale quantum computer. Therefore, it is essential to build a robust and secure cryptography algorithm against most vulnerable pre-quantum cryptography methods. That is called ‘Post Quantum Cryptography’. Therefore, the present crypto system needs to propose encryption key and signature size is very large.in addition to careful prediction of encryption/decryption time and amount of traffic over the communication wire is required. The post-quantum cryptography (PQC) article discusses different families of post-quantum cryptosystems, analyses the current status of the National Institute of Standards and Technology (NIST) post-quantum cryptography standardisation process, and looks at the difficulties faced by the PQC community.

Optimizing for periodicity: a model-independent approach to flux crosstalk calibration for superconducting circuits

Flux tunability is an important engineering resource for superconducting circuits. Large-scale quantum computers based on flux-tunable superconducting circuits face the problem of flux crosstalk, which needs to be accurately calibrated to realize high-fidelity quantum operations. Typical calibration methods either assume that circuit elements can be effectively decoupled and simple models can be applied, or require a large amount of data. Such methods become ineffective as the system size increases and circuit interactions become stronger. Here we propose a new method for calibrating flux crosstalk, which is independent of the underlying circuit model. Using the fundamental property that superconducting circuits respond periodically to external fluxes, crosstalk calibration of N flux channels can be treated as N independent optimization problems, with the objective functions being the periodicity of a measured signal depending on the compensation parameters. We demonstrate this method on a small-scale quantum annealing circuit based on superconducting flux qubits, achieving comparable accuracy with previous methods. We also show that the objective function usually has a nearly convex landscape, allowing efficient optimization.

Optical transmission of microwave control signal towards large-scale superconducting quantum computing.

With the rapid development of superconducting quantum computing and the implementation of surface code, large-scale quantum computing is emerging as an urgent demand. In a superconducting computing system, the qubit is maintained in a cryogenic environment to avoid thermal excitation. Thus, the transmission of control signals, which are generated at room temperature, is needed. Typically, the transmission of these signals to the qubit relies on a coaxial cable wiring approach. However, in a large-scale computing system with hundreds or even thousands of qubits, the coaxial cables will pose great space and heat load to the dilution refrigerator. Here, to tackle this problem, we propose and demonstrate a direct-modulation-based optical transmission line. In our experiment, the average single-qubit XEB error and control error are measured as 0.139% and 0.014% separately, demonstrating the feasibility of the optical wiring approach and paving the way for large-scale superconducting quantum computing.

Performance and Efficiency Exploration of Hardware Polynomial Multipliers for Post-Quantum Lattice-Based Cryptosystems

The significant effort in the research and design of large-scale quantum computers has spurred a transition to post-quantum cryptographic primitives worldwide. The post-quantum cryptographic primitive standardization effort led by the US NIST has recently selected the asymmetric encryption primitive Kyber as its candidate for standardization and indicated NTRU, as a valid alternative if intellectual property issues are not solved. Finally, a more conservative alternative to NTRU, NTRUPrime was also considered as an alternate candidate, due to its design choices that remove the possibility for a large set of attacks preemptively. All the aforementioned asymmetric primitives provide good performances, and are prime choices to provide IoT devices with post-quantum confidentiality services. In this work, we present a comprehensive exploration of hardware designs for the computation of polynomial multiplications, the workhorse operation in all the aforementioned cryptosystems, with a thorough analysis of performance, compactness and efficiency. The presented designs cope with the differences in the arithmetics of polynomial rings employed by distinct cryptosystems, benefiting from configurations and optimizations that are applicable at synthesis time and/or run time. In this context, we target a use case scenario where long-term key pairs are used, such as the ones for VPNs (e.g., over IPSec), secure shell protocols and instant messaging applications. Our high-performance design variants exhibit figures of latency comparable to the ones needed for the execution of the symmetric cryptographic primitives also included in the Post-Quantum schemes. Notably, the performance figures of the designs proposed for NTRU and NTRU Prime surpass the ones described in the related literature.

Logical quantum processor based on reconfigurable atom arrays

Suppressing errors is the central challenge for useful quantum computing1, requiring quantum error correction (QEC)2–6 for large-scale processing. However, the overhead in the realization of error-corrected ‘logical’ qubits, in which information is encoded across many physical qubits for redundancy2–4, poses substantial challenges to large-scale logical quantum computing. Here we report the realization of a programmable quantum processor based on encoded logical qubits operating with up to 280 physical qubits. Using logical-level control and a zoned architecture in reconfigurable neutral-atom arrays7, our system combines high two-qubit gate fidelities8, arbitrary connectivity7,9, as well as fully programmable single-qubit rotations and mid-circuit readout10–15. Operating this logical processor with various types of encoding, we demonstrate improvement of a two-qubit logic gate by scaling surface-code6 distance from d = 3 to d = 7, preparation of colour-code qubits with break-even fidelities5, fault-tolerant creation of logical Greenberger–Horne–Zeilinger (GHZ) states and feedforward entanglement teleportation, as well as operation of 40 colour-code qubits. Finally, using 3D [[8,3,2]] code blocks16,17, we realize computationally complex sampling circuits18 with up to 48 logical qubits entangled with hypercube connectivity19 with 228 logical two-qubit gates and 48 logical CCZ gates20. We find that this logical encoding substantially improves algorithmic performance with error detection, outperforming physical-qubit fidelities at both cross-entropy benchmarking and quantum simulations of fast scrambling21,22. These results herald the advent of early error-corrected quantum computation and chart a path towards large-scale logical processors.