Large Scale Integration Technology Research Articles

Artificial Amacrine Retinal Circuits.

Event-based imaging represents a new paradigm in visual information processing that addresses the speed and energy efficiency shortcomings inherently present in the current complementary metal oxide semiconductor-based machine vision. Realizing such imaging systems has previously been sought using very large-scale integration technologies that have complex circuitries consisting of many photodiodes, differential amplifiers, capacitors, and resistors. Here, we demonstrate that event-driven sensing can be achieved using a simple one-resistor, one-capacitor (1R1C) circuit, where the capacitor is modified with colloidal quantum dots (CQDs) to have a photoresponse. This sensory circuit emulates the motion-tracking function of the biological retina, in which the amacrine cells in the bipolar-to-ganglion synaptic pathway produce a transient spiking signal only in response to changes in light intensity but remain inactive under constant illumination. When extended to a 2D imaging array, the individual sensors work independently and output signals only when a change in the light intensity is detected; hence, the concept of the frame in image processing is thereby removed. In this work, we present the fabrication and characterization of a CQD photocapacitor-based 1R1C circuit that has a spectral response at 1550 nm in the short-wave infrared (SWIR). We report on the key performance parameters including peak responsivity, noise, and optical noise equivalent power and discuss the operating mechanism that is responsible for spiking responses in these artificial retinal circuits. The present work sets the foundation for expanding the bioinspired vision sensor capability toward midwave infrared (MWIR) and long-wave infrared (LWIR) spectral regions that are invisible to human eyes and mainstream semiconductor technologies.

Telecom Photon Emitters Based on Isolated Group-IV Quantum Dots Deterministically Coupled to High-Q Photonic Crystal Cavities

The realization of scalable telecom light emitters that can be monolithically implemented into large-scale Si integration technology has been a driving factor in the field of Si photonics for the last decades. Applications are envisioned in the short and medium-range data transfer and for realizing scalable, Si-based quantum information technology. For the latter, CMOS-compatible sources that can be controlled on the single photon level are needed. In solid-state materials, group-III-V quantum dots (QDs) are one of the leading platforms for realizing single photon emitters of excellent optical quality [1,2]. However, their emission outside the telecom band and the difficulty of combining them with the mature Si photonics components such as waveguides remain an ongoing problem.In the group-IV (SiGe) system, the bandgap of the bulk materials is indirect, and electron and hole states in QDs are spatially separated due to the type-II band alignment. These material properties lead to relatively long radiative lifetimes and small emission efficiencies. However, for Si/SiGe QDs grown on silicon on insulator substrates (SOI), these efficiencies can be strongly and deterministically Purcell-enhanced by aligning photonic crystal cavities with single QDs [3]. One necessary prerequisite is, therefore, to achieve perfect nucleation site control of the QDs on the substrates [4,5]. This nucleation control can be achieved by deterministic substrate patterning combined with Ge growth in the supersaturation regime of the two-dimensional wetting layer [6], utilizing Ge's extensive surface diffusion lengths at growth temperatures above 600°C [7]. In such a way, it is possible to grow isolated QDs with virtually arbitrary inter-QD distance [4,5].Here, one isolated QD was grown on a substrate area of the size of 100´100 µm2 [8]. We demonstrate the accurate QD positioning in PhC cavities [3,8], particularly in bichromatic cavities. Bichromatic cavities, a relatively novel design of photonic crystal cavity, offer ultra-high quality factor, and therefore Purcell enhancement, that is achievable with simple design rules [9]. Unlike in standard line defect cavities, in the present bichromatic layout, the line defect consists of a periodic sequence of holes, leaving only narrow Si regions.For this reason, an extremely high accuracy for QD positioning is required, which can be provided by interlacing site control of QD growth and PhC cavity formation. In micro photoluminescence spectra, the modes of single cavities are clearly observed. From the dependence of the mode intensities on the temperature and the excitation intensity, modes fed by the single QD in the cavity can be identified. We observe ultra-high quality factors of up to 100,000 for the modes coupled to QDs [8]. For resonators loaded with a QD, such high Q-factor values are record-high for the silicon-on-insulator integrated optics platform. Results on the excited state lifetime will be discussed.[1] D. Huber et al., Phys. Rev. Lett. 121, 33902 (2018)[2] N. Somaschi et al., Nature Photonics 10, 340 (2016)[3] M. Schatzl et al., ACS Photonics 4, 665 (2017)[4] M. Grydlik et al., Nanotechnology 24, 105601 (2013)[5] M. Brehm, et al., Nanotechnology 28, 392001 (2017)[6] M. Brehm, et al., Physical Review B 80 (20), 205321 (2009)[7] M. Grydlik et al., Physical Review B 88 (11), 115311 (2013)[8] T. Poempool et al., Optics Express 31 (10), 15564-15578 (2023)[9] A. Simbula et al., APL Photonics 2, 056102 (2017).

Certain investigation on hybrid neural network method for classification of ECG signal with the suitable a FIR filter

The Electrocardiogram (ECG) records are crucial for predicting heart diseases and evaluating patient’s health conditions. ECG signals provide essential peak values that reflect reliable health information. Analyzing ECG signals is a fundamental technique for computerized prediction with advancements in Very Large-Scale Integration (VLSI) technology and significantly impacts in biomedical signal processing. VLSI advancements focus on high-speed circuit functionality while minimizing power consumption and area occupancy. In ECG signal denoising, digital filters like Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) are commonly used. The FIR filters are preferred for their higher-order performance and stability over IIR filters, especially in real-time applications. The Modified FIR (MFIR) blocks were reconstructed using the optimized adder-multiplier block for better noise reduction performance. The MIT-BIT database is used as reference where the noises are filtered by the MFIR based on Optimized Kogge Stone Adder (OKSA). Features are extracted and analyzed using Discrete wavelet transform (DWT) and Cross Correlation (CC). At this modern era, Hybrid methods of Machine Learning (HMLM) methods are preferred because of their combined performance which is better than non-fused methods. The accuracy of the Hybrid Neural Network (HNN) model reached 92.3%, surpassing other models such as Generalized Sequential Neural Networks (GSNN), Artificial Neural Networks (ANN), Support Vector Machine with linear kernel (SVM linear), and Support Vector Machine with Radial Basis Function kernel (SVM RBF) by margins of 3.3%, 5.3%, 23.3%, and 24.3%, respectively. While the precision of the HNN is 91.1%, it was slightly lower than GSNN and ANN but higher than both SVM linear and SVM -RBF. The HNN with various features are incorporated to improve the ECG classification. The accuracy of the HNN is switched to 95.99% when the DWT and CC are combined. Also, it improvises other parameters such as precision 93.88%, recall is 0.94, F1 score is 0.88, Kappa is 0.89, kurtosis is 1.54, skewness is 1.52 and error rate 0.076. These parameters are higher than recently developed models whose algorithms and methods accuracy is more than 90%.

Synthesis of novel Stachytarpheta jamaicensis flower liked hexagonal boron nitride nanoribbons (SJF-BNNBs) to efficiently improve the thermal/mechanical/electrical properties of flexible polyimide films

Heat dissipation has become a bottleneck restricting large-scale integration and flexible electronic technologies. This study reports a novel fabrication strategy to prepare flexible stachytarpheta jamaicensis flower-like hexagonal boron nitride nanoribbons (SJF-BNNBs) and their composite films with polyimide (PI). The effect of synthesis conditions on the morphology of SJF-BNNBs was investigated, and the growth mechanism was proposed. The in-plane and through plane thermal conductivities of the 4 wt% SJF-BNNBs/PI composite film reach 5.98 W m−1 K−1 and 0.79 W m−1 K−1, which are 3047 % and 316 % higher than those of the pure PI film, respectively. The in-plane and through plane thermal conduction enhancement efficiencies reach 761.8 % and 78.9 %, respectively. The tensile strength of the composite film is 61.7 % higher than that of pure PI, and maintains excellent electrical insulating and thermal stability properties. Infrared imaging tests verified the excellent heat dissipation performance of the composite film as a thermal interface material and a flexible copper clad laminate substrate, where the operating temperature of device could be reduced by 17.3 °C. To the best of our knowledge, SJF-BNNBs outperform the most efficient thermally conductive electrically insulating filler and are to break the overcome of polymer composites in heat dissipation applications.

Implementation of Digital Filter Using Verilog HDL

Abstract: In the context of Very Large Scale Integration technology, where addition is essential, digital filters are essential elements. The performance of the Finite Impulse Response Filter is highly dependent on the speed of its multiplier unit, making itstand out among the others. In order to improve the effectiveness of the FIR filter, we suggest using a Wallace tree multiplier. This novel method offers improvements over conventional multipliers, with a decrease in latency being one of the main advantages. Significant improvements in latency are obtained by using Xilinx tools and implementing this filter design in Verilog HDL. The Wallace tree multiplier is perfect for FIR filter construction in low-voltage and low-power VLSI applications since it has benefits like higher operating frequency and reduced power consumption. This development might improve the effectiveness and performance of digital filters, especially in settings with limited resources, opening the way for more robust VLSI systems

Exploring the significance and applications of Field Programmable Gate Arrays in modern integrated circuits

In recent years, the rapid advancement of electronic technology and large-scale integrated circuit technology has led to increased integration of integrated circuits and expanding system scales on integrated motherboards. This evolution presents new challenges and demands in system design. Field Programmable Gate Arrays (FPGAs), a vital VLSI technology, have found extensive applications in communication, image processing, computers, and other domains, becoming a pivotal component of contemporary electronic systems. This paper aims to enhance the understanding of FPGAs by first delving into their theoretical foundations, followed by an overview of their general structural elements and a historical perspective on FPGA development. Additionally, this analyse and summarize relevant literature in the third section, focusing on the three primary application areas of FPGAs, elucidating their research processes and findings. Finally, the fourth section offers insights into the future directions of FPGA development, grounded in the current context. By acquainting readers with FPGAs essential attributes and its multifaceted applications, this paper underscores the pivotal role of FPGAs in the landscape of modern integrated circuits.

DESIGN AND IMPLEMENTATION OF A DIGITAL PHASE LOCKED LOOP FREQUENCY SYNTHESIZER IN THE L BAND

This paper proposes a design and implementation method of DPLL frequency synthesizer system. Such a system offers many advantages such as minimum complex architecture, low power consumption, and a maximum use of large scale integration technology. It can be used in many applications as cordless telephones, rnobile radios and other wireless products. A (2.4 - 3.6) GHz frequency range is designed and implemented with a 100KHz frequency step size. A spurious output levels of -70 dBc, an output power should be greater than 10 dBm, and a phase noise less then (-100) dBc/Hz at 100 kHz ofl'set from the carier are considered in our design. The channel selection is guided by digital gating circuits with thumbwheel switches. An option of PI\4 modulation of 5 MHz FM bandwidth is also included.

Open-source, multi-layer LSI design & fabrication framework for distributed IP development and education

Continuous development of Large Scale Integration (LSI) technologies based on Moore's law results in highly developed LSI technologies, as well as very high costs in design and fabrication and high design complexity. This fact prevents various users from contributing to the activities of designing LSIs, fabricating LSIs, and developing Intellectual Properties (IPs). On the other hand, the trend towards open-source has been attracting attention to overcome these problems and extend the potential of LSI technologies. The purpose of this research is to develop an open-source LSI design framework aimed at connecting various layers of LSI knowledge. Its methodology is composed of two parts. One is the development of the LSI design flow using existing open-source EDA tools and their related glue software. The other is the open-source, NDA-free PDK (process design kit) used in designing LSIs. The process of developing and constructing Large Scale Integrated (LSI) circuits within this framework is conducted and assessed. From these trials, the effect of enhancing educational effectiveness on LSI design is indicated. These trials enhanced the contributors’ interest and motivation to understand the details of computer systems and their relation to LSIs. It is also indicated that this framework is effective in enhancing rapid IP development as well as its importance as an educational aspect of open-source software.

Thermal Stability of Cu-Al-Ni Shape Memory Alloy Thin Films Obtained by Nanometer Multilayer Deposition.

Cu-Al-Ni is a high-temperature shape memory alloy (HTSMA) with exceptional thermomechanical properties, making it an ideal active material for engineering new technologies able to operate at temperatures up to 200 °C. Recent studies revealed that these alloys exhibit a robust superelastic behavior at the nanometer scale, making them excellent candidates for developing a new generation of micro-/nano-electromechanical systems (MEMS/NEMS). The very large-scale integration (VLSI) technologies used in microelectronics are based on thin films. In the present work, 1 μm thickness thin films of 84.1Cu-12.4 Al-3.5Ni (wt.%) were obtained by solid-state diffusion from a multilayer system deposited on SiNx (200 nm)/Si substrates by e-beam evaporation. With the aim of evaluating the thermal stability of such HTSMA thin films, heating experiments were performed in situ inside the transmission electron microscope to identify the temperature at which the material was decomposed by precipitation. Their microstructure, compositional analysis, and phase identification were characterized by scanning and transmission electron microscopy equipped with energy dispersive X-ray spectrometers. The nucleation and growth of two stable phases, Cu-Al-rich alpha phase and Ni-Al-rich intermetallic, were identified during in situ heating TEM experiments between 280 and 450 °C. These findings show that the used production method produces an HTSMA with high thermal stability and paves the road for developing high-temperature MEMS/NEMS using shape memory and superelastic technologies.

(Invited) High-Performance Field-Effect Transistors Based on Two-Dimensional Materials for VLSI Circuits

Introduction Nowadays, the scaling of silicon very large-scale integration(VLSI) technologies has reached channel thicknesses of 7nm. However, further downscaling becomes increasingly difficult as the gate electrostatics require a substantial reduction of the channel thickness to about a fourth of the gate length. As a result, the actual gate length of high-performance(HP) FETs at the current state-of-the-art amounts to 16nm and is projected to stall at 12nm for the 1.5nm node and the following nodes, according to the International Roadmap for Devices and Systems(IRDS)[1]. For these nodes, two-dimensional(2D) materials could have the potential to replace silicon as the channel material. They can maintain sizable mobilities at atomic thicknesses, thus providing enhanced gate control in stacked channel nanosheet transistor structures[2]. Even though FETs based on 2D materials hold the promise to serve as FETs at the front end of the line, numerous challenges still need to be overcome. Downscaling Dimensions For ultra-scaled device designs, 2D materials can be used as a channel in stacked nanosheet FETs. In such a structure, the 2D material is gated from both sides, as depicted in Fig.1(a). By stacking multiple double-gated channels on top of each other, the required on-current density of around 1mA/μm can be achieved[3]. The first experimental demonstrations have achieved sub-5nm gate lengths[4] or, in a different design, a gate pitch of only 42nm[5], meeting the requirements for the 1.5nm node. While these prototypes show that 2D FETs can be scaled down, they have been fabricated in a laboratory. Many challenges must be overcome before such small devices can be fabricated in industry-compatible batch processes which require a high yield and low variability. Contact Engineering In order to enable sufficiently high on-current densities, small contact resistances to 2D semiconductors are required, which are inhibited by the formation of Schottky barriers at the metal to semiconductor interface. Schottky contacts to 2D materials are so prevalent because there is, on one side, a lack of stable doping schemes, and on the other side, pronounced Fermi-level pinning at the metal-to-semiconductor interface. Semi-metallic bismuth contacts can provide low-resistive contacts to n-type MoS2 FETs, as the bismuth suppresses the metal-induced gap states which pin the Fermi-level[6]. This way, a small contact resistance of 123Ωμm has been achieved, reaching the IRDS limit for the 1.5nm node. While comparable results have been realized for antimony contacts to n-type FETs, low-resistive contacts to p-type FETs are more challenging. Gate Stack Design A good gate stack for 2D FETs must provide excellent gate control while maintaining small gate leakage currents, which requires a capacitive equivalent thickness(CET) smaller than 0.9 nm. At these small CETs, a small gate leakage can only be obtained with a high-dielectric constant gate insulator and sizable band offsets, rendering some insulators, e.g. hexagonal boron nitride, unsuitable. Simultaneously, the gate insulator should form a van-der Waals interface with the 2D semiconductor, as otherwise, interface traps degrade the carrier mobility and the sub-threshold slope[7]. Charge traps within the insulator are the root cause of the limited stability and reliability of 2D FETs, as seen by a large hysteresis in the transfer characteristics or in pronounced Bias Temperature Instabilities(BTI). The electrical stability can be improved, if the defect bands in the gate insulator are energetically far away from the semiconductor’s conduction and valence band edges, see Fig.1(b)[8]. Conclusions Despite all the progress achieved within the last decade, the challenges for VLSI integration of 2D materials are enormous. First, stacked 2D FETs with scaled dimensions still need to be realized at an industrial scale. Second, despite low contact resistance demonstrations for n-type FETs, the resistances for p-type FETs are one order of magnitude too high. Finally, one of the most serious obstacles is identifying a suitable gate stack. Even though promising combinations of insulators to semiconductors have been suggested, like Bi2O5Se/Bi2O2Se, CaF2/MoS2 or SrTiO3/MoS2, it is at the moment unclear, which of them provides the best performance. Acknowledgments The authors thank for funding from the European Research Council under grant agreement no. 101055379.

Ultimate Limit in Optoelectronic Performances of Monolayer WSe2 Sloping-Channel Transistors.

Atomically thin monolayer two-dimensional (2D) semiconductors with natural immunity to short channel effects are promising candidates for sub-10 nm very large-scale integration technologies. Herein, the ultimate limit in optoelectronic performances of monolayer WSe2 field-effect transistors (FETs) is examined by constructing a sloping channel down to 6 nm. Using a simple scaling method compatible with current micro/nanofabrication technologies, we achieve a record high saturation current up to 1.3 mA/μm at room temperature, surpassing any reported monolayer 2D semiconductor transistors. Meanwhile, quasi-ballistic transport in WSe2 FETs is first demonstrated; the extracted high saturation velocity of 4.2 × 106 cm/s makes it suitable for extremely sensitive photodetectors. Furthermore, the photoresponse speed can be improved by reducing channel length due to an electric field-assisted detrapping process of photogenerated carriers in localized states. As a result, the sloping-channel device exhibits a faster response, higher detectivity, and additional polarization resolution ability compared to planar micrometer-scale devices.

Interpretable machine learning in VLSI physical design

Today's popularisation of portable devices largely depends on the progress in integrated circuits. Modern Very Large Scale Integration technology (VLSI) allows billions of transistors to be packed into the same chip. In the past years, digital design in VLSI has been developed compared to analogue design. The traditional method is hard to model the performance change in analogue or mixed-signal components caused by physical design. In the early 2000s, rapid advances in machine learning and computing power made analogue design automation possible. Despite their outstanding performance, the transparency issue has become significant. This paper introduces the history of VLSI physical design, which includes placement and routing in the early stages. The change that machine learning (ML) has made is mentioned in the third section. Analysis of the potential problem has been proposed, followed by a brief category of some well-known work in interpretable Machine Learning, which could be the primary direction for VLSI automation to be further popularised in the future.

A systematic and bibliometric review of the latest techniques in quantum-dot computers

When designing and manufacturing logic circuits, minimal energy loss, high packing densities, and functioning at Tera-hertz frequencies are highly sought characteristics. Due to the rapid growth of large-scale integration technology, producing a dependable architecture with minimal power consumption is crucial. Quantum dot Cellular Automata (QCA) is a potential substitute to the traditional semiconductor-based technique for constructing logic circuits in the nano-scale range due to the promising implementation of these highly desired properties. QCA cells may be used to create arbitrary circuits by following a few straightforward layout criteria. In contrast to conventional computers, quantum computers work faster by utilizing the principles of quantum physics. It is crucial to consider what applications these devices may aid, given that quantum computing technologies are on the cusp of commercialization and quantum dominance. As a result, this paper offers a thorough and bibliometric assessment of the most recent quantum-dot computing methods. In order to present some intriguing directions for any future study, it provides the benefits and drawbacks of the evaluated mechanisms and their significant problems. According to the results, reversible logic in QCA may be regarded as one of the most hopeful technologies for next-generation computers.

Local Manipulation of Skyrmion Nucleation in Microscale Areas of a Thin Film with Nitrogen-Ion Implantation.

Precise manipulation of skyrmion nucleation in microscale or nanoscale areas of thin films is a critical issue in developing high-efficient skyrmionic memories and logic devices. Presently, the mainstream controlling strategies focus on the application of external stimuli to tailor the intrinsic attributes of charge, spin, and lattice. This work reports effective skyrmion manipulation by controllably modifying the lattice defect through ion implantation, which is potentially compatible with large-scale integrated circuit technology. By implanting an appropriate dose of nitrogen ions into a Pt/Co/Ta multilayer film, the defect density was effectively enhanced to induce an apparent modulation of magnetic anisotropy, consequently boosting the skyrmion nucleation. Furthermore, the local control of skyrmions in microscale areas of the macroscopic film was realized by combining the ion implantation with micromachining technology, demonstrating a potential application in both binary storage and multistate storage. These findings provide a new approach to advancing the functionalization and application of skyrmionic devices.

Micromechanical valve-operated needle-on-a-chip microinjection module for microfluidic large-scale integration

Microinjection is an essential process in genetic engineering that is used to deliver genetic materials into various biological specimens. Considering the high-throughput requirement for microinjection applications ranging from gene editing to cell therapies, there is a need for an automated, highly parallelized, reproducible, and easy-to-use microinjection strategy. Here we report an on-chip, microfluidic microinjection module designed for compatibility with microfluidic large-scale integration technology that can be fabricated via standard, multilayer soft lithography techniques. The needle-on-chip (NOC) module consists of a two-layer polydimethylsiloxane-based microfluidic module whose puncture and injection operations are reliant solely on Quake valve actuation. As a proof-of-concept, we designed a NOC module to conduct the microinjection of a common genetics model organism, Caenorhabditis elegans (C. elegans). The NOC design was analyzed using finite element method simulations for a large range of practically viable geometrical parameters. The computational results suggested that a slight lateral offset (>10 μm) of the control channel is sufficient for a successful NOC operation with a large fabrication tolerance (50 μm, 50% channel width). To demonstrate proof-of-concept, the microinjection platform was fabricated and utilized to perform a successful injection of a tracer dye into C. elegans.

Advancement and Challenges of Biosensing Using Field Effect Transistors.

Field-effect transistors (FETs) have become eminent electronic devices for biosensing applications owing to their high sensitivity, faster response and availability of advanced fabrication techniques for their production. The device physics of this sensor is now well understood due to the emergence of several numerical modelling and simulation papers over the years. The pace of advancement along with the knowhow of theoretical concepts proved to be highly effective in detecting deadly pathogens, especially the SARS-CoV-2 spike protein of the coronavirus with the onset of the (coronavirus disease of 2019) COVID-19 pandemic. However, the advancement in the sensing system is also accompanied by various hurdles that degrade the performance. In this review, we have explored all these challenges and how these are tackled with innovative approaches, techniques and device modifications that have also raised the detection sensitivity and specificity. The functional materials of the device are also structurally modified towards improving the surface area and minimizing power dissipation for developing miniaturized microarrays applicable in ultra large scale integration (ULSI) technology. Several theoretical models and simulations have also been carried out in this domain which have given a deeper insight on the electron transport mechanism in these devices and provided the direction for optimizing performance.

Hybrid Design of Pseudo Random Number Generator Using Shift Register FPGA and CMOS VLSI

The proliferation of digital systems in various applications necessitates the development of efficient pseudo-random number generators (PRNGs) for cryptographic and data processing purposes. In this study, we present a novel approach to PRNG design, leveraging a hybrid combination of Shift Register Field-Programmable Gate Arrays (FPGA) and Complementary Metal-Oxide-Semiconductor (CMOS) Very Large-Scale Integration (VLSI) technology. This hybrid design capitalizes on the strengths of both FPGA and CMOS VLSI to achieve enhanced performance and versatility. The FPGA-based component of the PRNG system offers configurability and parallelism, allowing for rapid and customizable PRNG generation. The CMOS VLSI component, on the other hand, ensures low power consumption and compact integration, ideal for embedded applications. By combining these two technologies, the PRNG achieves a delicate balance between flexibility and efficiency. We evaluate the hybrid PRNG design through rigorous testing and analysis, including statistical tests, spectral tests, and computational performance assessments. Our results demonstrate that the hybrid PRNG outperforms standalone FPGA or CMOS-based PRNGs in terms of randomness, uniformity, and speed, making it suitable for a wide range of applications in cryptography, secure communications, and data processing. The hybrid PRNG design presented in this study not only contributes to the advancement of PRNG technology but also offers a versatile solution for engineers and researchers seeking to tailor their PRNG systems to specific application requirements while optimizing performance and energy efficiency.

Current trends and future perspective of designing on-chip antennas

AbstractWith the evolution of 5G and 6G network architectures, the demand for highly compact system-on-chip-based devices with high data transfer capabilities has been increased significantly. While the advancement of very large-scale integration technology with the continuous scaling of complementary metal–oxide–semiconductor nodes put forward to integrate different functional modules of a complete system on a single IC board, the antenna being the largest component still remains outside of the chip. Integration of the antenna and other functional modules of a system on the same chip leads to produce a really compact and economical design. Though on-chip antenna (OCAs) have several other advantages and emerging applications, they have some design challenges in terms of low gain due to losses in the substrate, requirement of miniaturization at lower microwave frequencies (LMFs) (particularly, below 10 GHz), unavailability of proper design rules, etc. In this paper, analyzing the design challenges of OCAs, their current research trends and future perspective applications are discussed.

Fault-Tolerant Strong Menger (Edge) Connectivity of DCC Linear Congruential Graphs

With the rapid development and advances of very large scale integration technology and wafer-scale integration technology, multiprocessor systems, taking interconnection networks as underlying topologies, have been widely designed and used in big data era. The topology of an interconnection network is usually represented as a graph. If any two distinct vertices [Formula: see text] in a connected graph [Formula: see text] are connected by min[Formula: see text] vertex (edge)-disjoint paths, then [Formula: see text] is called strongly Menger (edge) connected. In 1996, Opatrny et al. [16] introduced the DCC (Disjoint Consecutive Cycle) linear congruential graph, which consists of [Formula: see text] nodes and is generated by a set of linear functions [Formula: see text] with special properties. In this work, we investigate the strong Menger connectivity of the DCC linear congruential graph [Formula: see text] with faulty vertices or edges, where [Formula: see text], [Formula: see text], gcd[Formula: see text] and [Formula: see text] is a multiple of [Formula: see text]. In detail, we show that [Formula: see text] is strongly Menger connected if [Formula: see text] for any [Formula: see text]. Moreover, we determine that [Formula: see text] is strongly Menger edge connected if [Formula: see text] for any [Formula: see text]. Furthermore, we prove that, under the restricted condition [Formula: see text], [Formula: see text] is strongly Menger edge connected if [Formula: see text] and [Formula: see text] for any [Formula: see text]. In addition, we present some empirical examples to show that the bounds are all optimal in the sense of the maximum number of tolerable edge faults.

Low-Resistivity Cobalt and Ruthenium Ultra-Thin Film Deposition Using Bipolar HiPIMS Technique

Owing to the rapid growth of very large-scale integration technology at nanometer scales, cobalt and ruthenium interconnects are being used to solve the high-resistivity copper problem. However, with such interconnects, carbon contamination can occur during chemical vapor deposition and atomic layer deposition. Bipolar (BP) high-power impulse magnetron sputtering (HiPIMS) with a high ionization rate is an excellent vacuum process for depositing low-resistivity thin films. In this study, low-resistivity cobalt, ruthenium, and copper thin films were deposited using BP-HiPIMS, HiPIMS, and direct-current magnetron sputtering (DCMS). The resistivities of the cobalt, ruthenium, and copper thin films (<10 nm) deposited via BP-HiPIMS were 91.5, 75, and 35%, respectively, lower than the resistivities of the same film materials deposited using direct-current MS. To solve the low pass-through flux of cobalt, the target temperature was raised to the Curie temperature (approximately 1100 °C) using a thermal insulation backplate (Ti-6Al-4V), resulting in a resistivity reduction of about 73%. The study provides a novel method for the vacuum deposition of cobalt and ruthenium thin films.